Line 27... |
Line 27... |
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//
|
//
|
module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid);
|
module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
|
|
o_illegal);
|
|
parameter IMPLEMENT_MPY = 1;
|
input i_clk, i_rst, i_ce;
|
input i_clk, i_rst, i_ce;
|
input [3:0] i_op;
|
input [3:0] i_op;
|
input [31:0] i_a, i_b;
|
input [31:0] i_a, i_b;
|
input i_valid;
|
input i_valid;
|
output reg [31:0] o_c;
|
output reg [31:0] o_c;
|
output wire [3:0] o_f;
|
output wire [3:0] o_f;
|
output reg o_valid;
|
output reg o_valid;
|
|
output wire o_illegal;
|
|
|
wire [63:0] w_rol_tmp;
|
wire [63:0] w_rol_tmp;
|
assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
|
assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
|
wire [31:0] w_rol_result;
|
wire [31:0] w_rol_result;
|
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
|
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
|
|
`ifndef NEW_NOT_OLD_CODE
|
wire [33:0] w_lsr_result, w_asr_result;
|
wire [33:0] w_lsr_result, w_asr_result;
|
wire signed [33:0] w_ia_input;
|
wire signed [33:0] w_ia_input;
|
assign w_ia_input = { i_a[31], i_a, 1'b0 };
|
assign w_ia_input = { i_a[31], i_a, 1'b0 };
|
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
|
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
|
: ( w_ia_input >>> (i_b[4:0]) );// ASR
|
: ( w_ia_input >>> (i_b[4:0]) );// ASR
|
assign w_lsr_result = (|i_b[31:5])? 34'h00
|
assign w_lsr_result = (|i_b[31:5])? 34'h00
|
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
|
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
|
|
`else
|
|
wire [32:0] w_lsr_result, w_asr_result;
|
|
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
|
|
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
|
|
assign w_lsr_result = (|i_b[31:5])? 33'h00
|
|
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
|
|
`endif
|
|
|
|
|
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
|
|
wire signed [33:0] w_mpy_result;
|
|
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
|
|
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
|
|
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
|
|
|
|
wire z, n, v;
|
wire z, n, v;
|
reg c, pre_sign, set_ovfl;
|
reg c, pre_sign, set_ovfl;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_ce)
|
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
|
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
|
&&(i_a[31] != i_b[31]))
|
&&(i_a[31] != i_b[31]))
|
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
|
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
|
||(i_op == 4'hd) // LSL
|
||(i_op == 4'hd) // LSL
|
||(i_op == 4'hf)); // LSR
|
||(i_op == 4'hf)); // LSR
|
|
|
|
generate
|
|
if (IMPLEMENT_MPY == 0)
|
|
begin
|
|
always @(posedge i_clk)
|
|
if (i_ce)
|
|
begin
|
|
pre_sign <= (i_a[31]);
|
|
c <= 1'b0;
|
|
casez(i_op)
|
|
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
|
|
4'b?001: o_c <= i_a & i_b; // BTST/And
|
|
4'h5: o_c <= w_rol_result; // ROL
|
|
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
|
|
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
|
|
4'ha: { c, o_c } <= i_a + i_b; // Add
|
|
4'hb: o_c <= i_a | i_b; // Or
|
|
4'hc: o_c <= i_a ^ i_b; // Xor
|
|
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
|
|
4'he: { o_c, c } <= w_asr_result[32:0];// ASR
|
|
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
|
|
default: o_c <= i_b; // MOV, LDI
|
|
endcase
|
|
end
|
|
end else begin
|
|
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
|
|
wire signed [33:0] w_mpy_result;
|
|
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
|
|
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
|
|
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_ce)
|
begin
|
begin
|
pre_sign <= (i_a[31]);
|
pre_sign <= (i_a[31]);
|
c <= 1'b0;
|
c <= 1'b0;
|
Line 86... |
Line 122... |
4'he: { o_c, c } <= w_asr_result[32:0];// ASR
|
4'he: { o_c, c } <= w_asr_result[32:0];// ASR
|
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
|
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
|
default: o_c <= i_b; // MOV, LDI
|
default: o_c <= i_b; // MOV, LDI
|
endcase
|
endcase
|
end
|
end
|
|
end endgenerate
|
|
|
|
generate
|
|
if (IMPLEMENT_MPY == 0)
|
|
begin
|
|
reg r_illegal;
|
|
always @(posedge i_clk)
|
|
r_illegal <= (i_op == 4'h3)||(i_op == 4'h4);
|
|
assign o_illegal = r_illegal;
|
|
end else
|
|
assign o_illegal = 1'b0;
|
|
endgenerate
|
|
|
assign z = (o_c == 32'h0000);
|
assign z = (o_c == 32'h0000);
|
assign n = (o_c[31]);
|
assign n = (o_c[31]);
|
assign v = (set_ovfl)&&(pre_sign != o_c[31]);
|
assign v = (set_ovfl)&&(pre_sign != o_c[31]);
|
|
|
Line 97... |
Line 145... |
|
|
initial o_valid = 1'b0;
|
initial o_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
o_valid <= 1'b0;
|
o_valid <= 1'b0;
|
else if (i_ce)
|
else
|
o_valid <= i_valid;
|
o_valid <= (i_ce)&&(i_valid);
|
else if (~i_ce)
|
|
o_valid <= 1'b0;
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|