| Line 39... |
Line 39... |
output reg [31:0] o_c;
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output reg [31:0] o_c;
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output wire [3:0] o_f;
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output wire [3:0] o_f;
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output reg o_valid;
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output reg o_valid;
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output wire o_illegal;
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output wire o_illegal;
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// Rotate-left pre-logic
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wire [63:0] w_rol_tmp;
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wire [63:0] w_rol_tmp;
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
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wire [31:0] w_rol_result;
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wire [31:0] w_rol_result;
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
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`ifndef NEW_NOT_OLD_CODE
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wire [33:0] w_lsr_result, w_asr_result;
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// Shift register pre-logic
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wire signed [33:0] w_ia_input;
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assign w_ia_input = { i_a[31], i_a, 1'b0 };
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assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
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: ( w_ia_input >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 34'h00
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: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
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`else
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wire [32:0] w_lsr_result, w_asr_result;
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wire [32:0] w_lsr_result, w_asr_result;
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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assign w_lsr_result = (|i_b[31:5])? 33'h00
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
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`endif
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wire z, n, v;
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wire z, n, v;
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reg c, pre_sign, set_ovfl;
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reg c, pre_sign, set_ovfl;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 70... |
Line 63... |
&&(i_a[31] != i_b[31]))
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&&(i_a[31] != i_b[31]))
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||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
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||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
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||(i_op == 4'hd) // LSL
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||(i_op == 4'hd) // LSL
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||(i_op == 4'hf)); // LSR
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||(i_op == 4'hf)); // LSR
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// A 4-way multiplexer can be done in one 6-LUT.
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// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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// the Xilinx multiplexer fabric that follows.
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// Given that we wish to apply this multiplexer approach to 33-bits,
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// this will cost a minimum of 132 6-LUTs.
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generate
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generate
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if (IMPLEMENT_MPY == 0)
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if (IMPLEMENT_MPY == 0)
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begin
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begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
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4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'b?001: o_c <= i_a & i_b; // BTST/And
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// 4'h3: There's a hole here for the unimplemented MPYU,
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// 4'h4: and here for the unimplemented MPYS
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4'h5: o_c <= w_rol_result; // ROL
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4'h5: o_c <= w_rol_result; // ROL
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hb: o_c <= i_a | i_b; // Or
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| Line 94... |
Line 95... |
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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end else begin
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end else begin
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//
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// Multiply pre-logic
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//
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [33:0] w_mpy_result;
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wire signed [33:0] w_mpy_result;
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assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
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assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
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assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
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assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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//
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// The master ALU case statement
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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pre_sign <= (i_a[31]);
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pre_sign <= (i_a[31]);
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c <= 1'b0;
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c <= 1'b0;
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casez(i_op)
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casez(i_op)
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4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
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4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'b?001: o_c <= i_a & i_b; // BTST/And
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4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
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4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
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4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
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4'h5: o_c <= w_rol_result; // ROL
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4'h5: o_c <= w_rol_result; // ROL
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hb: o_c <= i_a | i_b; // Or
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| Line 129... |
Line 137... |
generate
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generate
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if (IMPLEMENT_MPY == 0)
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if (IMPLEMENT_MPY == 0)
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begin
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begin
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reg r_illegal;
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reg r_illegal;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_illegal <= (i_op == 4'h3)||(i_op == 4'h4);
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r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
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assign o_illegal = r_illegal;
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assign o_illegal = r_illegal;
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end else
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end else
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assign o_illegal = 1'b0;
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assign o_illegal = 1'b0;
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endgenerate
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endgenerate
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