| Line 73... |
Line 73... |
output wire [31:0] o_I;
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output wire [31:0] o_I;
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output reg o_zI;
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output reg o_zI;
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output reg [3:0] o_cond;
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output reg [3:0] o_cond;
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output reg o_wF;
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output reg o_wF;
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output reg [3:0] o_op;
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output reg [3:0] o_op;
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output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
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output reg o_ALU, o_M, o_DV, o_FP, o_break;
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output wire o_lock;
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output reg o_wR, o_rA, o_rB;
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output reg o_wR, o_rA, o_rB;
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output wire o_early_branch;
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output wire o_early_branch;
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output wire [(AW-1):0] o_branch_pc;
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output wire [(AW-1):0] o_branch_pc;
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output wire o_ljmp;
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output wire o_ljmp;
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output reg o_pipe;
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output reg o_pipe;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire o_dcd_early_branch;
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wire o_dcd_early_branch;
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wire [(AW-1):0] o_dcd_branch_pc;
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wire [(AW-1):0] o_dcd_branch_pc;
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reg o_dcdI, o_dcdIz;
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reg o_dcdI, o_dcdIz;
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`ifdef OPT_PIPELINED
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reg r_lock;
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`endif
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wire [4:0] w_op;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire [3:0] w_cond;
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wire [3:0] w_cond;
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| Line 121... |
Line 125... |
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assign w_op= iword[26:22];
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assign w_op= iword[26:22];
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assign w_mov = (w_op == 5'h0f);
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assign w_mov = (w_op == 5'h0f);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_ldi = (w_op[4:1] == 4'hb);
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assign w_brev = (w_op == 5'hc);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_cmptst = (w_op[4:1] == 4'h8);
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assign w_ldixx = (w_op[4:1] == 4'h4);
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assign w_ldilo = (w_op[4:0] == 5'h9);
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assign w_ALU = (~w_op[4]);
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assign w_ALU = (~w_op[4]);
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// 4 LUTs
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// 4 LUTs
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assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
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assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
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iword[30:27] };
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iword[30:27] };
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| Line 174... |
Line 179... |
||((w_dcdM)&&(w_op[0]))
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||((w_dcdM)&&(w_op[0]))
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// Test/compares
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// Test/compares
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||(w_op[4:1]== 4'h8);
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||(w_op[4:1]== 4'h8);
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// 1 LUTs -- do we read a register for operand B? Specifically, do
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// 1 LUTs -- do we read a register for operand B? Specifically, do
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// we need to stall if the register is not (yet) ready?
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// we need to stall if the register is not (yet) ready?
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assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
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assign w_rB = (w_mov)||((iword[18])&&(~w_ldi));
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||(w_cmptst);
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||(w_cmptst);
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assign w_wR = ~w_wR_n;
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assign w_wR = ~w_wR_n;
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| Line 187... |
Line 192... |
//
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//
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// and writes to the PC/CC register(s).
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// and writes to the PC/CC register(s).
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assign w_wF = (w_cmptst)
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assign w_wF = (w_cmptst)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_ALU)&&(~w_mov)&&(~w_ldixx)
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||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev)
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&&(iword[30:28] != 3'h7))));
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&&(iword[30:28] != 3'h7))));
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// Bottom 13 bits: no LUT's
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// Bottom 13 bits: no LUT's
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[ 13] -- 2 LUTs
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// w_dcd[ 13] -- 2 LUTs
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| Line 270... |
Line 275... |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
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else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
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o_illegal <= 1'b1;
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o_illegal <= 1'b1;
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if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
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if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
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&&(
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&&(
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(w_op[2:0] != 3'h2) // LOCK
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(w_op[2:0] != 3'h1) // BREAK
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&&(w_op[2:0] != 3'h1) // BREAK
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`ifdef OPT_PIPELINED
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&&(w_op[2:0] != 3'h2) // LOCK
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`endif
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&&(w_op[2:0] != 3'h0))) // NOOP
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&&(w_op[2:0] != 3'h0))) // NOOP
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o_illegal <= 1'b1;
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o_illegal <= 1'b1;
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end
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end
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| Line 330... |
Line 337... |
o_M <= w_dcdM;
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o_M <= w_dcdM;
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o_DV <= w_dcdDV;
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o_DV <= w_dcdDV;
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o_FP <= w_dcdFP;
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o_FP <= w_dcdFP;
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o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
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o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
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o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
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`ifdef OPT_PIPELINED
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r_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
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`endif
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`ifdef OPT_VLIW
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`ifdef OPT_VLIW
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r_nxt_half <= { iword[31], iword[13:5],
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r_nxt_half <= { iword[31], iword[13:5],
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((iword[21])? iword[20:19] : 2'h0),
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((iword[21])? iword[20:19] : 2'h0),
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iword[4:0] };
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iword[4:0] };
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`endif
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`endif
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end
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end
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`ifdef OPT_PIPELINED
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assign o_lock = r_lock;
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`else
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assign o_lock = 1'b0;
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`endif
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generate
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generate
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if (EARLY_BRANCHING!=0)
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if (EARLY_BRANCHING!=0)
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begin
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begin
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reg r_early_branch, r_ljmp;
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reg r_early_branch, r_ljmp;
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reg [(AW-1):0] r_branch_pc;
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reg [(AW-1):0] r_branch_pc;
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| Line 414... |
Line 429... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
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&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
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&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
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&&(i_instruction[17:14] == o_dcdB[3:0])
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&&(i_instruction[17:14] == o_dcdB[3:0])
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&&(i_instruction[17:14] != o_dcdA[3:0])
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&&(i_gie == o_gie)
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&&(i_gie == o_gie)
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&&((i_instruction[21:19]==o_cond[2:0])
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&&((i_instruction[21:19]==o_cond[2:0])
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||(o_cond[2:0] == 3'h0))
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||(o_cond[2:0] == 3'h0))
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&&((i_instruction[13:0]==r_I[13:0])
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&&((i_instruction[13:0]==r_I[13:0])
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||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
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||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
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