| Line 53... |
Line 53... |
//
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//
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//
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//
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module idecode(i_clk, i_rst, i_ce, i_stalled,
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module idecode(i_clk, i_rst, i_ce, i_stalled,
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i_instruction, i_gie, i_pc, i_pf_valid,
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i_instruction, i_gie, i_pc, i_pf_valid,
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i_illegal,
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i_illegal,
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o_valid,
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o_phase, o_illegal,
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o_phase, o_illegal,
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o_pc, o_gie,
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o_pc, o_gie,
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o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
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o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
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o_cond, o_wF,
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o_cond, o_wF,
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o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
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o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
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| Line 70... |
Line 71... |
input i_clk, i_rst, i_ce, i_stalled;
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input i_clk, i_rst, i_ce, i_stalled;
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input [31:0] i_instruction;
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input [31:0] i_instruction;
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input i_gie;
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input i_gie;
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input [(AW-1):0] i_pc;
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input [(AW-1):0] i_pc;
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input i_pf_valid, i_illegal;
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input i_pf_valid, i_illegal;
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output wire o_phase;
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output wire o_valid, o_phase;
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output reg o_illegal;
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output reg o_illegal;
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output reg [AW:0] o_pc;
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output reg [AW:0] o_pc;
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output reg o_gie;
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output reg o_gie;
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output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
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output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
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output wire [31:0] o_I;
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output wire [31:0] o_I;
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| Line 103... |
Line 104... |
reg r_pipe;
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reg r_pipe;
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`endif
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`endif
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wire [4:0] w_op;
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wire [4:0] w_op;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
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wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev,
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w_noop, w_lock;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire [4:0] w_dcdR, w_dcdB, w_dcdA;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdR_pc, w_dcdR_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdA_pc, w_dcdA_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire w_dcdB_pc, w_dcdB_cc;
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wire [3:0] w_cond;
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wire [3:0] w_cond;
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wire w_wF, w_mem, w_sto, w_lod, w_div, w_fpu;
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wire w_wF, w_mem, w_sto, w_div, w_fpu;
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wire w_wR, w_rA, w_rB, w_wR_n;
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wire w_wR, w_rA, w_rB, w_wR_n;
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wire w_ljmp, w_ljmp_dly, w_cis_ljmp;
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wire w_ljmp, w_ljmp_dly, w_cis_ljmp;
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wire [31:0] iword;
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wire [31:0] iword;
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| Line 215... |
Line 217... |
// 2 LUTs
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// 2 LUTs
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//
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//
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// If the result register is either CC or PC, and this would otherwise
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// If the result register is either CC or PC, and this would otherwise
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// be a floating point instruction with floating point opcode of 0,
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// be a floating point instruction with floating point opcode of 0,
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// then this is a NOOP.
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// then this is a NOOP.
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assign w_lock = (!iword[31])&&(w_op[4:0]==5'h1d)&&(
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
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||(IMPLEMENT_FPU==0));
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assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
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assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
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||(IMPLEMENT_FPU==0));
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||(IMPLEMENT_FPU==0));
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// dcdB - What register is used in the opB?
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// dcdB - What register is used in the opB?
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| Line 250... |
Line 255... |
{ (iword[21:19]==3'h0), iword[21:19] };
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{ (iword[21:19]==3'h0), iword[21:19] };
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// 1 LUT
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// 1 LUT
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assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
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assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
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assign w_sto = (w_mem)&&( w_cis_op[0]);
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assign w_sto = (w_mem)&&( w_cis_op[0]);
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assign w_lod = (w_mem)&&(!w_cis_op[0]);
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// 1 LUT
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// 1 LUT
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assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7);
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assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7);
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// 2 LUTs
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// 2 LUTs
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assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11)
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assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11)
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&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
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&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
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| Line 401... |
Line 405... |
begin
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begin
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`ifdef OPT_CIS
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`ifdef OPT_CIS
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if (!o_phase)
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if (!o_phase)
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o_gie<= i_gie;
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o_gie<= i_gie;
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if ((iword[31])&&(!o_phase))
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if (iword[31])
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begin
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if (o_phase)
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o_pc <= o_pc + 1'b1;
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else if (i_pf_valid)
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o_pc <= { i_pc, 1'b1 };
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o_pc <= { i_pc, 1'b1 };
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else if ((iword[31])&&(i_pf_valid))
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end else begin
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o_pc <= { i_pc, 1'b0 };
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// The normal, non-CIS case
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else
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o_pc <= { i_pc + 1'b1, 1'b0 };
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o_pc <= { i_pc + 1'b1, 1'b0 };
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end
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`else
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`else
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o_gie<= i_gie;
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o_gie<= i_gie;
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o_pc <= { i_pc + 1'b1, 1'b0 };
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o_pc <= { i_pc + 1'b1, 1'b0 };
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`endif
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`endif
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| Line 458... |
Line 466... |
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o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
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o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
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||(IMPLEMENT_FPU==0));
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||(IMPLEMENT_FPU==0));
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`ifdef OPT_PIPELINED
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`ifdef OPT_PIPELINED
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r_lock <= (!iword[31])&&(w_op[4:0]==5'h1d)&&(
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r_lock <= w_lock;
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((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
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||(IMPLEMENT_FPU==0));
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`endif
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`endif
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`ifdef OPT_CIS
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`ifdef OPT_CIS
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r_nxt_half <= { iword[31], iword[14:0] };
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r_nxt_half <= { iword[31], iword[14:0] };
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`endif
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`endif
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| Line 586... |
Line 592... |
`endif
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_valid <= 1'b0;
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r_valid <= 1'b0;
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else if ((i_ce)&&(o_ljmp))
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else if (i_ce)
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r_valid <= 1'b0;
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r_valid <= ((i_pf_valid)||(o_phase)||(i_illegal))
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else if ((i_ce)&&(i_pf_valid))
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&&(!o_ljmp)&&(!o_early_branch);
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r_valid <= 1'b1;
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else if (!i_stalled)
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else if (~i_stalled)
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r_valid <= 1'b0;
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r_valid <= 1'b0;
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assign o_valid = r_valid;
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assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
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assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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