| Line 125... |
Line 125... |
iword[17:14] };
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iword[17:14] };
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// 0 LUTs
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// 0 LUTs
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assign w_dcdA = w_dcdR;
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assign w_dcdA = w_dcdR;
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// 2 LUTs, 1 delay each
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// 2 LUTs, 1 delay each
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assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
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// assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
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assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
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assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
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// 0 LUTs
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// 0 LUTs
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assign w_dcdA_pc = w_dcdR_pc;
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assign w_dcdA_pc = w_dcdR_pc;
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assign w_dcdA_cc = w_dcdR_cc;
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assign w_dcdA_cc = w_dcdR_cc;
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// 2 LUTs, 1 delays each
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// 2 LUTs, 1 delays each
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| Line 170... |
Line 170... |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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assign w_wR_n = ((w_dcdM)&&(w_op[0]))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
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||(w_cmptst);
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||(w_cmptst);
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assign w_wR = ~w_wR_n;
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assign w_wR = ~w_wR_n;
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// 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits)
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//
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// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
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//
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//
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// This'd be 4 LUTs, save that we have the carve out for NOOPs
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// and writes to the PC/CC register(s).
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assign w_wF = (w_cmptst)
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assign w_wF = (w_cmptst)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
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||((w_ALU)&&(~w_mov)&&(~w_ldixx))));
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||((w_ALU)&&(~w_mov)&&(~w_ldixx)
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&&(iword[30:28] != 3'h7))));
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// Bottom 13 bits: no LUT's
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// Bottom 13 bits: no LUT's
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[12: 0] -- no LUTs
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// w_dcd[ 13] -- 2 LUTs
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// w_dcd[ 13] -- 2 LUTs
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// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
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// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
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| Line 332... |
Line 335... |
if (EARLY_BRANCHING!=0)
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if (EARLY_BRANCHING!=0)
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begin
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begin
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reg r_early_branch;
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reg r_early_branch;
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reg [(AW-1):0] r_branch_pc;
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reg [(AW-1):0] r_branch_pc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3]))
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if (i_ce)
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begin
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begin
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if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc))
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if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
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begin // Move (X+PC) to PC
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begin
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r_early_branch <= 1'b1;
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if (w_op[4:1] == 4'hb) // LDI to PC
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end else if (w_op[4:1] == 4'hb) // LDI to PC
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begin // LDI x,PC
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begin // LDI x,PC
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r_early_branch <= 1'b1;
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r_early_branch <= 1'b1;
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end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc))
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end else if ((w_op[4:0]==5'h02)&&(~iword[18]))
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begin // Add x,PC
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begin // Add x,PC
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r_early_branch <= 1'b1;
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r_early_branch <= 1'b1;
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end else begin
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end else begin
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r_early_branch <= 1'b0;
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r_early_branch <= 1'b0;
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end
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end
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end else begin
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end else
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if (i_ce)
|
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r_early_branch <= 1'b0;
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r_early_branch <= 1'b0;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_ce)
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if (i_ce)
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begin
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begin
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if (w_op[4:1] == 4'hb)
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if (w_op[4:1] == 4'hb) // LDI
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r_branch_pc <= {{(AW-23){w_I[22]}},w_I};
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r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
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else
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else // Add x,PC
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r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I}
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r_branch_pc <= i_pc
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+ {{(AW-18){iword[17]}},iword[16:0]}
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+{{(AW-1){1'b0}},1'b1};
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+{{(AW-1){1'b0}},1'b1};
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end
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end
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|
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assign o_early_branch = r_early_branch;
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assign o_early_branch = r_early_branch;
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assign o_branch_pc = r_branch_pc;
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assign o_branch_pc = r_branch_pc;
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