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// In the interests of code simplicity, this memory operator is
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// In the interests of code simplicity, this memory operator is
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// susceptible to unknown results should a new command be sent to it
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// susceptible to unknown results should a new command be sent to it
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// before it completes the last one. Unpredictable results might then
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// before it completes the last one. Unpredictable results might then
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// occurr.
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// occurr.
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//
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//
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// 20150919 -- Added support for handling BUS ERR's (i.e., the WB
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// error signal).
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module memops(i_clk, i_rst, i_stb,
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module memops(i_clk, i_rst, i_stb,
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i_op, i_addr, i_data, i_oreg,
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i_op, i_addr, i_data, i_oreg,
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o_busy, o_valid, o_wreg, o_result,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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i_wb_ack, i_wb_stall, i_wb_data);
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_stb;
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input i_stb;
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// CPU interface
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// CPU interface
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input i_op;
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input i_op;
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input [31:0] i_addr;
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input [31:0] i_addr;
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input [31:0] i_data;
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input [31:0] i_data;
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input [4:0] i_oreg;
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input [4:0] i_oreg;
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// CPU outputs
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// CPU outputs
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output wire o_busy;
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output wire o_busy;
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output reg o_valid;
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output reg o_valid;
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output reg o_err;
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output reg [4:0] o_wreg;
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output reg [4:0] o_wreg;
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output reg [31:0] o_result;
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output reg [31:0] o_result;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc, o_wb_stb, o_wb_we;
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output reg o_wb_cyc_gbl, o_wb_stb_gbl;
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output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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output reg [31:0] o_wb_addr, o_wb_data;
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output reg [31:0] o_wb_addr, o_wb_data;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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o_wb_cyc <= 1'b0;
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begin
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else if (o_wb_cyc)
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc <= (~i_wb_ack);
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o_wb_cyc_lcl <= 1'b0;
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else if (i_stb) // New memory operation
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end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
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// Grab the wishbone
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begin
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o_wb_cyc <= 1'b1;
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if ((i_wb_ack)||(i_wb_err))
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begin
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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end
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end else if (i_stb) // New memory operation
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begin // Grab the wishbone
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o_wb_cyc_lcl <= lcl_stb;
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o_wb_cyc_gbl <= gbl_stb;
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (o_wb_cyc)
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if (o_wb_cyc_gbl)
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o_wb_stb <= (o_wb_stb)&&(i_wb_stall);
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o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
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else
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else
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o_wb_stb <= i_stb; // Grab wishbone on new operation
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o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
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always @(posedge i_clk)
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if (o_wb_cyc_lcl)
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o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
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else
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o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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begin
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begin
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o_wb_we <= i_op;
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o_wb_we <= i_op;
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o_wb_data <= i_data;
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o_wb_data <= i_data;
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o_wb_addr <= i_addr;
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o_wb_addr <= i_addr;
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end
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end
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we);
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o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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assign o_busy = o_wb_cyc;
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initial o_err = 1'b0;
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always @(posedge i_clk)
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o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
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assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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o_wreg <= i_oreg;
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o_wreg <= i_oreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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