| Line 42... |
Line 42... |
o_busy, o_valid, o_err, o_wreg, o_result,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_stb;
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input i_stb;
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// CPU interface
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// CPU interface
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input i_op;
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input i_op;
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input [31:0] i_addr;
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input [31:0] i_addr;
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| Line 58... |
Line 59... |
output reg [4:0] o_wreg;
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output reg [4:0] o_wreg;
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output reg [31:0] o_result;
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output reg [31:0] o_result;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc_gbl, o_wb_stb_gbl;
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output reg o_wb_cyc_gbl, o_wb_stb_gbl;
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output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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output reg [31:0] o_wb_addr, o_wb_data;
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output reg [(AW-1):0] o_wb_addr;
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output reg [31:0] o_wb_data;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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|
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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| Line 99... |
Line 101... |
always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stb)
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if (i_stb)
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begin
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begin
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o_wb_we <= i_op;
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o_wb_we <= i_op;
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o_wb_data <= i_data;
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o_wb_data <= i_data;
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o_wb_addr <= i_addr;
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o_wb_addr <= i_addr[(AW-1):0];
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end
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end
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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