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//
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//
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// 20150919 -- Added support for handling BUS ERR's (i.e., the WB
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// 20150919 -- Added support for handling BUS ERR's (i.e., the WB
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// error signal).
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// error signal).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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| Line 35... |
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module memops(i_clk, i_rst, i_stb,
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module memops(i_clk, i_rst, i_stb, i_lock,
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i_op, i_addr, i_data, i_oreg,
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i_op, i_addr, i_data, i_oreg,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_busy, o_valid, o_err, o_wreg, o_result,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_cyc_gbl, o_wb_cyc_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
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parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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input i_stb;
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input i_stb, i_lock;
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// CPU interface
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// CPU interface
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input i_op;
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input i_op;
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input [31:0] i_addr;
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input [31:0] i_addr;
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input [31:0] i_data;
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input [31:0] i_data;
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input [4:0] i_oreg;
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input [4:0] i_oreg;
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| Line 57... |
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output reg o_valid;
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output reg o_valid;
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output reg o_err;
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output reg o_err;
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output reg [4:0] o_wreg;
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output reg [4:0] o_wreg;
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output reg [31:0] o_result;
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output reg [31:0] o_result;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc_gbl, o_wb_stb_gbl;
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output wire o_wb_cyc_gbl;
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output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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output reg o_wb_stb_gbl;
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output wire o_wb_cyc_lcl;
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output reg o_wb_stb_lcl;
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output reg o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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reg r_wb_cyc_gbl, r_wb_cyc_lcl;
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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initial r_wb_cyc_gbl = 1'b0;
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initial r_wb_cyc_lcl = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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o_wb_cyc_gbl <= 1'b0;
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r_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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r_wb_cyc_lcl <= 1'b0;
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end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
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end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
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begin
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begin
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if ((i_wb_ack)||(i_wb_err))
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if ((i_wb_ack)||(i_wb_err))
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begin
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begin
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o_wb_cyc_gbl <= 1'b0;
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r_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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r_wb_cyc_lcl <= 1'b0;
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end
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end
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end else if (i_stb) // New memory operation
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end else if (i_stb) // New memory operation
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begin // Grab the wishbone
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begin // Grab the wishbone
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o_wb_cyc_lcl <= lcl_stb;
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r_wb_cyc_lcl <= lcl_stb;
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o_wb_cyc_gbl <= gbl_stb;
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r_wb_cyc_gbl <= gbl_stb;
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (o_wb_cyc_gbl)
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if (o_wb_cyc_gbl)
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o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
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o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
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else
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else
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| Line 118... |
Line 124... |
if (i_stb)
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if (i_stb)
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o_wreg <= i_oreg;
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o_wreg <= i_oreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_ack)
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if (i_wb_ack)
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o_result <= i_wb_data;
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o_result <= i_wb_data;
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generate
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if (IMPLEMENT_LOCK != 0)
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begin
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reg lock_gbl, lock_lcl;
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initial lock_gbl = 1'b0;
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initial lock_lcl = 1'b0;
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always @(posedge i_clk)
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begin
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lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
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lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
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end
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assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
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assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
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end else begin
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assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
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assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
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end endgenerate
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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