| Line 72... |
Line 72... |
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reg [(AW-1):0] lastpc;
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reg [(AW-1):0] lastpc;
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reg [(CW-1):0] rdaddr;
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reg [(CW-1):0] rdaddr;
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reg [(AW-1):CW] tagval;
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reg [(AW-1):CW] tagval;
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wire [(AW-1):PW] lasttag;
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wire [(AW-1):PW] lasttag;
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reg illegal_valid;
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reg [(AW-1):PW] illegal_cache;
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reg [(AW-1):PW] illegal_cache;
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initial o_i = 32'h76_00_00_00; // A NOOP instruction
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initial o_i = 32'h76_00_00_00; // A NOOP instruction
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initial o_pc = 0;
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initial o_pc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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| Line 93... |
Line 94... |
always @(posedge i_clk)
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always @(posedge i_clk)
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// It may be possible to recover a clock once the cache line
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// It may be possible to recover a clock once the cache line
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// has been filled, but our prior attempt to do so has lead
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// has been filled, but our prior attempt to do so has lead
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// to a race condition, so we keep this logic simple.
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// to a race condition, so we keep this logic simple.
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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lastpc <= tags[i_pc[(CW-1):PW]];
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tagval <= tags[i_pc[(CW-1):PW]];
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else
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else
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tagval <= tags[lastpc[(CW-1):PW]];
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tagval <= tags[lastpc[(CW-1):PW]];
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// i_pc will only increment when everything else isn't stalled, thus
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// i_pc will only increment when everything else isn't stalled, thus
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// we can set it without worrying about that. Doing this enables
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// we can set it without worrying about that. Doing this enables
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| Line 153... |
Line 154... |
begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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end else if (o_wb_cyc)
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end else if (o_wb_cyc)
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begin
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begin
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if ((o_wb_stb)&&(~i_wb_stall))
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if (i_wb_err)
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o_wb_stb <= 1'b0;
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else if ((o_wb_stb)&&(~i_wb_stall))
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begin
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begin
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if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
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if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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else
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else
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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end
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end
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if (i_wb_ack)
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if (i_wb_ack)
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begin
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begin
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rdaddr <= rdaddr + 1;
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rdaddr <= rdaddr + 1;
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if (rdaddr[(PW-1):0] == {(PW){1'b1}})
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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end
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end
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if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
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if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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| Line 177... |
Line 179... |
// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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end else if ((~r_v)&&(delay==0)
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end else if ((~r_v)&&(delay==0)
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&&((tagval != lastpc[(AW-1):CW])
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&&((tagval != lastpc[(AW-1):CW])
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||(~vmask[lastpc[(CW-1):PW]]))
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||(~vmask[lastpc[(CW-1):PW]]))
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&&(~o_illegal))
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&&((~illegal_valid)||(lastpc[(AW-1):PW] != illegal_cache)))
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begin
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begin
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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| Line 202... |
Line 204... |
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
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vmask[rdaddr[(CW-1):PW]] <= 1'b1;
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if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
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if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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end
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end
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reg illegal_valid;
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initial illegal_cache = 0;
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initial illegal_cache = 0;
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initial illegal_valid = 0;
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initial illegal_valid = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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illegal_cache <= 0;
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illegal_cache <= 0;
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illegal_valid <= 0;
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illegal_valid <= 0;
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end else if ((o_wb_cyc)&&(i_wb_err))
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end else if ((o_wb_cyc)&&(i_wb_err))
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begin
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begin
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illegal_cache <= lastpc[(AW-1):PW];
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illegal_cache <= o_wb_addr[(AW-1):PW];
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illegal_valid <= 1'b1;
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illegal_valid <= 1'b1;
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end
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end
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initial o_illegal = 1'b0;
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initial o_illegal = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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o_illegal <= 1'b0;
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o_illegal <= 1'b0;
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else
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else
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o_illegal <= (illegal_valid)
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o_illegal <= (illegal_valid)
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&&(tagval == i_pc[(AW-1):CW])
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&&(illegal_cache == i_pc[(AW-1):PW]);
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&&(illegal_cache == i_pc[(AW-1):PW]);
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endmodule
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endmodule
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