| Line 98... |
Line 98... |
// us to work in spite of stalls. For example, if the next address
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// us to work in spite of stalls. For example, if the next address
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// isn't valid, but the decoder is stalled, get the next address
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// isn't valid, but the decoder is stalled, get the next address
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// anyway.
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// anyway.
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initial lastpc = 0;
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initial lastpc = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((r_v)||(i_clear_cache)||(i_new_pc))
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if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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lastpc <= i_pc;
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lastpc <= i_pc;
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initial lasttag = 0;
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initial lasttag = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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lasttag <= i_pc[(AW-1):PW];
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lasttag <= i_pc[(AW-1):PW];
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| Line 118... |
Line 118... |
reg [1:0] delay;
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reg [1:0] delay;
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initial delay = 2'h3;
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initial delay = 2'h3;
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initial r_v = 1'b0;
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initial r_v = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache)||(i_new_pc)||(r_v))
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if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
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begin
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begin
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r_v <= r_v_from_pc;
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r_v <= r_v_from_pc;
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delay <= 2'h2;
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delay <= 2'h2;
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end else begin
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end else if (~r_v) begin // Otherwise, r_v was true and we were
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r_v <= r_v_from_last;
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r_v <= r_v_from_last; // stalled, hence only if ~r_v
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if (o_wb_cyc)
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if (o_wb_cyc)
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delay <= 2'h2;
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delay <= 2'h2;
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else if (delay != 0)
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else if (delay != 0)
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delay <= delay - 1;
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delay <= delay - 1;
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end
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end
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| Line 164... |
Line 164... |
// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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|
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end else if ((~r_v)&&(delay==0)
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end else if ((~r_v)&&(delay==0)
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&&((tagval != lastpc[(AW-1):CW])
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&&((tagval != lastpc[(AW-1):CW])
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||(~vmask[lastpc[(CW-1):PW]])))
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||(~vmask[lastpc[(CW-1):PW]]))
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&&(~o_illegal))
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begin
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begin
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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| Line 187... |
Line 188... |
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
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else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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vmask[lastpc[(CW-1):PW]] <= 1'b0;
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else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
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else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
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vmask[rdaddr[(CW-1):PW]] <= 1'b1;
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vmask[rdaddr[(CW-1):PW]] <= 1'b1;
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|
|
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reg illegal_valid;
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initial illegal_cache = 0;
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initial illegal_cache = 0;
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initial illegal_valid = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
|
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begin
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illegal_cache <= 0;
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illegal_cache <= 0;
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else if ((o_wb_cyc)&&(i_wb_err))
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illegal_valid <= 0;
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end else if ((o_wb_cyc)&&(i_wb_err))
|
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begin
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illegal_cache <= lastpc[(AW-1):PW];
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illegal_cache <= lastpc[(AW-1):PW];
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illegal_valid <= 1'b1;
|
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end
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|
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initial o_illegal = 1'b0;
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initial o_illegal = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stall_n)
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if ((i_rst)||(i_clear_cache))
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o_illegal <= (illegal_cache == lastpc[(AW-1):PW]);
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o_illegal <= 1'b0;
|
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else
|
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o_illegal <= (illegal_valid)
|
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&&(tagval == i_pc[(AW-1):CW])
|
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&&(illegal_cache == i_pc[(AW-1):PW]);
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|
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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