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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
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module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
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o_i, o_pc, o_v,
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o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
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parameter RESET_ADDRESS=32'h0010_0000,
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parameter RESET_ADDRESS=32'h0010_0000,
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LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
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LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
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BUSW=32;
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BUSW=32;
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input i_clk, i_rst, i_new_pc, i_stall_n;
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input i_clk, i_rst, i_new_pc,
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i_clear_cache, i_stall_n;
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input [(BUSW-1):0] i_pc;
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input [(BUSW-1):0] i_pc;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_pc;
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output reg [(BUSW-1):0] o_pc;
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output wire o_v;
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output wire o_v;
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//
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//
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+ (1<<(LGCACHELEN-1)));
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+ (1<<(LGCACHELEN-1)));
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initial r_nvalid = 0;
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initial r_nvalid = 0;
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_rst)
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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// r_cache_base <= RESET_ADDRESS;
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// r_cache_base <= RESET_ADDRESS;
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// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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// &&(i_pc >= r_cache_base)
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// &&(i_pc >= r_cache_base)
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// &&(i_pc < r_cache_base + bus_nvalid))
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// &&(i_pc < r_cache_base + bus_nvalid))
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// begin
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// begin
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end
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end
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end
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end
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst) // Required, so we can reload memoy and then reset
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if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
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r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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else if ((o_wb_cyc)&&(i_wb_ack))
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else if ((o_wb_cyc)&&(i_wb_ack))
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r_nvalid <= r_nvalid+1;
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r_nvalid <= r_nvalid+1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_wb_cyc)&&(
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if (i_clear_cache)
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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r_cache_base <= i_pc;
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_wb_cyc)&&(
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if (i_clear_cache)
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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r_cache_offset <= 0;
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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r_cache_offset <= 0;
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r_cache_offset <= 0;
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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else if ((~o_wb_cyc)&&(w_running_out_of_cache))
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r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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if (i_clear_cache)
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o_wb_addr <= i_pc;
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else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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||(w_ran_off_end_of_cache)))
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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o_wb_addr <= o_wb_addr + 1;
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o_wb_addr <= o_wb_addr + 1;
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cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
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cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
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<= i_wb_data;
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<= i_wb_data;
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initial r_addr_set = 1'b0;
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initial r_addr_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if ((i_rst)||(i_clear_cache))
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r_addr_set <= 1'b0;
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r_addr_set <= 1'b0;
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else if (i_new_pc)
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else if (i_new_pc)
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r_addr_set <= 1'b1;
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r_addr_set <= 1'b1;
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// Now, read from the cache
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// Now, read from the cache
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Line 249... |
o_i <= cache[c_rdaddr];
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o_i <= cache[c_rdaddr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stall_n)
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if (i_stall_n)
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o_pc <= r_addr;
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o_pc <= r_addr;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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