| Line 12... |
Line 12... |
// these results so that we have them before we need them, then
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// these results so that we have them before we need them, then
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// we have a chance of keeping our CPU from stalling. Those are
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// we have a chance of keeping our CPU from stalling. Those are
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// the purposes of this instruction fetch module: 1) Pipeline
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// the purposes of this instruction fetch module: 1) Pipeline
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// wishbone accesses, and 2) an instruction cache.
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// wishbone accesses, and 2) an instruction cache.
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//
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//
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// 20150919 -- Fixed a nasty race condition whereby the pipefetch routine
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// would produce either the same instruction twice, or skip
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// an instruction. This condition was dependent on the CPU stall
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// condition, and would only take place if the pipeline wasn't
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// completely full throughout the stall.
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//
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// Interface support was also added for trapping on illegal
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// instructions (i.e., instruction fetches that cause bus errors),
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// however the internal interface has not caught up to supporting
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// these exceptions yet.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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| Line 38... |
Line 49... |
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
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module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
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o_i, o_pc, o_v,
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o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
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o_illegal);
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parameter RESET_ADDRESS=32'h0010_0000,
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parameter RESET_ADDRESS=32'h0010_0000,
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LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
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LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
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BUSW=32;
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BUSW=32;
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input i_clk, i_rst, i_new_pc,
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input i_clk, i_rst, i_new_pc,
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i_clear_cache, i_stall_n;
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i_clear_cache, i_stall_n;
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| Line 54... |
Line 66... |
output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [(BUSW-1):0] o_wb_addr;
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output reg [(BUSW-1):0] o_wb_addr;
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output wire [(BUSW-1):0] o_wb_data;
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output wire [(BUSW-1):0] o_wb_data;
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//
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//
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [(BUSW-1):0] i_wb_data;
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input [(BUSW-1):0] i_wb_data;
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//
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//
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// Is the (data) memory unit also requesting access to the bus?
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// Is the (data) memory unit also requesting access to the bus?
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input i_wb_request;
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input i_wb_request;
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output wire o_illegal;
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assign o_illegal = 1'b0;
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// Fixed bus outputs: we read from the bus only, never write.
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// Fixed bus outputs: we read from the bus only, never write.
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// Thus the output data is ... irrelevant and don't care. We set it
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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// to zero just to set it to something.
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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| Line 91... |
Line 106... |
||(r_addr >= r_cache_base + CACHELEN)));
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||(r_addr >= r_cache_base + CACHELEN)));
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wire w_running_out_of_cache;
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wire w_running_out_of_cache;
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assign w_running_out_of_cache = (r_addr_set)
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assign w_running_out_of_cache = (r_addr_set)
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&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
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&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
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+ (1<<(LGCACHELEN-1)));
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+ (1<<(LGCACHELEN-1)));
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initial r_nvalid = 0;
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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| Line 159... |
Line 173... |
if (i_wb_ack)
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if (i_wb_ack)
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begin
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begin
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// r_nvalid <= r_nvalid + 1;
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// r_nvalid <= r_nvalid + 1;
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if ((r_acks_waiting == 1)&&(~o_wb_stb))
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if ((r_acks_waiting == 1)&&(~o_wb_stb))
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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end
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end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
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o_wb_cyc <= 1'b0;
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end
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end
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end
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end
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initial r_nvalid = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
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if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
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r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
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| Line 208... |
Line 224... |
initial r_acks_waiting = 0;
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initial r_acks_waiting = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_cyc)
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if (~o_wb_cyc)
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r_acks_waiting <= 0;
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r_acks_waiting <= 0;
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else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);
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r_acks_waiting <= r_acks_waiting + 1;
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else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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r_acks_waiting <= r_acks_waiting - 1;
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r_acks_waiting <= r_acks_waiting - 1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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| Line 230... |
Line 246... |
wire w_cv; // Cache valid, address is in the cache
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wire w_cv; // Cache valid, address is in the cache
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reg r_cv;
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reg r_cv;
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assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
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assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
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&&(r_addr-r_cache_base < bus_nvalid));
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&&(r_addr-r_cache_base < bus_nvalid));
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_cv <= (~i_new_pc)&&(w_cv);
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r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
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assign o_v = (r_cv)&&(~i_new_pc);
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assign o_v = (r_cv)&&(~i_new_pc);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_new_pc)
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if (i_new_pc)
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r_addr <= i_pc;
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r_addr <= i_pc;
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else if ((i_stall_n)&&(w_cv))
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else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
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r_addr <= r_addr + 1;
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r_addr <= r_addr + 1;
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|
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wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
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wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
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assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
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assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
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assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
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assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stall_n)
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if ((~o_v)||((i_stall_n)&&(o_v)))
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o_i <= cache[c_rdaddr];
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o_i <= cache[c_rdaddr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_stall_n)
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if ((~o_v)||((i_stall_n)&&(o_v)))
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o_pc <= r_addr;
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o_pc <= r_addr;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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