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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Diff between revs 36 and 38
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| Rev 36 |
Rev 38 |
| Line 213... |
Line 213... |
r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_clear_cache)
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if (i_clear_cache)
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o_wb_addr <= i_pc;
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o_wb_addr <= i_pc;
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else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
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begin
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if (i_wb_ack)
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o_wb_addr <= r_cache_base + bus_nvalid+1;
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else
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o_wb_addr <= r_cache_base + bus_nvalid;
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end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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||(w_ran_off_end_of_cache)))
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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o_wb_addr <= o_wb_addr + 1;
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o_wb_addr <= o_wb_addr + 1;
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initial r_acks_waiting = 0;
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initial r_acks_waiting = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_cyc)
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if (~o_wb_cyc)
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r_acks_waiting <= 0;
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r_acks_waiting <= 0;
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else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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r_acks_waiting <= r_acks_waiting + 1;
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r_acks_waiting <= r_acks_waiting + 1;
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else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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r_acks_waiting <= r_acks_waiting - 1;
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r_acks_waiting <= r_acks_waiting - 1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
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cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
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