| Line 52... |
Line 52... |
o_i, o_pc, o_v,
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o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
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o_illegal);
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o_illegal);
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parameter RESET_ADDRESS=32'h0010_0000,
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parameter RESET_ADDRESS=32'h0010_0000,
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LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
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LGCACHELEN = 6, ADDRESS_WIDTH=24,
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BUSW=32;
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CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_new_pc,
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input i_clk, i_rst, i_new_pc,
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i_clear_cache, i_stall_n;
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i_clear_cache, i_stall_n;
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input [(BUSW-1):0] i_pc;
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input [(AW-1):0] i_pc;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_pc;
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output reg [(AW-1):0] o_pc;
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output wire o_v;
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output wire o_v;
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//
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//
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output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [(BUSW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output wire [(BUSW-1):0] o_wb_data;
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output wire [(BUSW-1):0] o_wb_data;
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//
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//
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [(BUSW-1):0] i_wb_data;
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input [(BUSW-1):0] i_wb_data;
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//
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//
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| Line 81... |
Line 81... |
// Thus the output data is ... irrelevant and don't care. We set it
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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// to zero just to set it to something.
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 0;
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assign o_wb_data = 0;
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reg [(BUSW-1):0] r_cache_base;
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reg [(AW-1):0] r_cache_base;
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reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
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reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
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reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
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reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
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reg [(LGCACHELEN-1):0] r_cache_offset;
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reg [(LGCACHELEN-1):0] r_cache_offset;
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|
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reg r_addr_set;
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reg r_addr_set;
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reg [(BUSW-1):0] r_addr;
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reg [(AW-1):0] r_addr;
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|
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wire [(BUSW-1):0] bus_nvalid;
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wire [(AW-1):0] bus_nvalid;
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assign bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
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assign bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
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|
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// What are some of the conditions for which we need to restart the
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// What are some of the conditions for which we need to restart the
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// cache?
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// cache?
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wire w_pc_out_of_bounds;
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wire w_pc_out_of_bounds;
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assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
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assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
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||(i_pc < r_cache_base)
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||(i_pc < r_cache_base)
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||(i_pc >= r_cache_base + CACHELEN)));
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||(i_pc >= r_cache_base + CACHELEN)
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||(i_pc >= r_cache_base + bus_nvalid+5)));
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wire w_ran_off_end_of_cache;
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wire w_ran_off_end_of_cache;
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assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
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assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
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||(r_addr >= r_cache_base + CACHELEN)));
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||(r_addr >= r_cache_base + CACHELEN)
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||(r_addr >= r_cache_base + bus_nvalid+5)));
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wire w_running_out_of_cache;
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wire w_running_out_of_cache;
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assign w_running_out_of_cache = (r_addr_set)
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assign w_running_out_of_cache = (r_addr_set)
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&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
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&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
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+ (1<<(LGCACHELEN-1)));
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+ (1<<(LGCACHELEN-1)))
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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|
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache))
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begin
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begin
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