| Line 73... |
Line 73... |
//
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//
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// Is the (data) memory unit also requesting access to the bus?
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// Is the (data) memory unit also requesting access to the bus?
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input i_wb_request;
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input i_wb_request;
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output wire o_illegal;
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output wire o_illegal;
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assign o_illegal = 1'b0;
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// Fixed bus outputs: we read from the bus only, never write.
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// Fixed bus outputs: we read from the bus only, never write.
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// Thus the output data is ... irrelevant and don't care. We set it
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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// to zero just to set it to something.
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 0;
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assign o_wb_data = 0;
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| Line 117... |
Line 115... |
&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
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initial r_cache_base = RESET_ADDRESS;
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initial r_cache_base = RESET_ADDRESS;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((i_rst)||(i_clear_cache))
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if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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// r_cache_base <= RESET_ADDRESS;
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// r_cache_base <= RESET_ADDRESS;
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// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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| Line 186... |
Line 184... |
end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
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end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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end
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end
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end
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end
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initial r_nvalid = 0;
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initial r_nvalid = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
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if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
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r_nvalid <= 0;
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r_nvalid <= 0;
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else if ((~o_wb_cyc)&&(
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else if ((~o_wb_cyc)&&(
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| Line 236... |
Line 235... |
else
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else
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o_wb_addr <= r_cache_base + bus_nvalid;
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o_wb_addr <= r_cache_base + bus_nvalid;
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end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
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||(w_ran_off_end_of_cache)))
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||(w_ran_off_end_of_cache)))
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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else if ((o_wb_stb)&&(~i_wb_stall)) // && o_wb_cyc
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o_wb_addr <= o_wb_addr + 1;
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o_wb_addr <= o_wb_addr + 1;
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initial r_acks_waiting = 0;
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initial r_acks_waiting = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_cyc)
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if (~o_wb_cyc)
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r_acks_waiting <= 0;
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r_acks_waiting <= 0;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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// o_wb_cyc *must* be true for all following
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else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
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r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
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r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
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else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
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r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
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r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
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cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
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| Line 285... |
Line 285... |
o_i <= cache[c_rdaddr];
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o_i <= cache[c_rdaddr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((~o_v)||((i_stall_n)&&(o_v)))
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if ((~o_v)||((i_stall_n)&&(o_v)))
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o_pc <= r_addr;
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o_pc <= r_addr;
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reg [(AW-1):0] ill_address;
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initial ill_address = 0;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_err))
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ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
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|
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assign o_illegal = (o_pc == ill_address);
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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