| Line 11... |
Line 11... |
// clock. This renders on-chip memory fast enough to handle single cycle
|
// clock. This renders on-chip memory fast enough to handle single cycle
|
// (pipelined) access.
|
// (pipelined) access.
|
//
|
//
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Tecnology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
//
|
//
|
| Line 33... |
Line 33... |
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
//
|
//
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////
|
//
|
//
|
module pipemem(i_clk, i_rst, i_pipe_stb,
|
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
|
i_op, i_addr, i_data, i_oreg,
|
i_op, i_addr, i_data, i_oreg,
|
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
|
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
|
o_wb_cyc_gbl, o_wb_cyc_lcl,
|
o_wb_cyc_gbl, o_wb_cyc_lcl,
|
o_wb_stb_gbl, o_wb_stb_lcl,
|
o_wb_stb_gbl, o_wb_stb_lcl,
|
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
|
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
|
parameter ADDRESS_WIDTH = 24, AW=ADDRESS_WIDTH;
|
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
input i_pipe_stb;
|
input i_pipe_stb, i_lock;
|
// CPU interface
|
// CPU interface
|
input i_op;
|
input i_op;
|
input [31:0] i_addr;
|
input [31:0] i_addr;
|
input [31:0] i_data;
|
input [31:0] i_data;
|
input [4:0] i_oreg;
|
input [4:0] i_oreg;
|
| Line 56... |
Line 56... |
output reg o_valid;
|
output reg o_valid;
|
output reg o_err;
|
output reg o_err;
|
output reg [4:0] o_wreg;
|
output reg [4:0] o_wreg;
|
output reg [31:0] o_result;
|
output reg [31:0] o_result;
|
// Wishbone outputs
|
// Wishbone outputs
|
output reg o_wb_cyc_gbl, o_wb_stb_gbl;
|
output wire o_wb_cyc_gbl;
|
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
|
output reg o_wb_stb_gbl;
|
|
output wire o_wb_cyc_lcl;
|
|
output reg o_wb_stb_lcl, o_wb_we;
|
output reg [(AW-1):0] o_wb_addr;
|
output reg [(AW-1):0] o_wb_addr;
|
output reg [31:0] o_wb_data;
|
output reg [31:0] o_wb_data;
|
// Wishbone inputs
|
// Wishbone inputs
|
input i_wb_ack, i_wb_stall, i_wb_err;
|
input i_wb_ack, i_wb_stall, i_wb_err;
|
input [31:0] i_wb_data;
|
input [31:0] i_wb_data;
|
|
|
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
|
reg [3:0] rdaddr, wraddr;
|
reg [3:0] rdaddr, wraddr;
|
wire [3:0] nxt_rdaddr;
|
wire [3:0] nxt_rdaddr;
|
reg [(5-1):0] fifo_oreg [0:15];
|
reg [(5-1):0] fifo_oreg [0:15];
|
initial rdaddr = 0;
|
initial rdaddr = 0;
|
initial wraddr = 0;
|
initial wraddr = 0;
|
| Line 90... |
Line 93... |
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
|
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
|
assign gbl_stb = (~lcl_stb);
|
assign gbl_stb = (~lcl_stb);
|
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
|
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
|
|
|
initial cyc = 0;
|
initial cyc = 0;
|
initial o_wb_cyc_lcl = 0;
|
initial r_wb_cyc_lcl = 0;
|
initial o_wb_cyc_gbl = 0;
|
initial r_wb_cyc_gbl = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
begin
|
begin
|
o_wb_cyc_gbl <= 1'b0;
|
r_wb_cyc_gbl <= 1'b0;
|
o_wb_cyc_lcl <= 1'b0;
|
r_wb_cyc_lcl <= 1'b0;
|
o_wb_stb_gbl <= 1'b0;
|
o_wb_stb_gbl <= 1'b0;
|
o_wb_stb_lcl <= 1'b0;
|
o_wb_stb_lcl <= 1'b0;
|
cyc <= 1'b0;
|
cyc <= 1'b0;
|
end else if (cyc)
|
end else if (cyc)
|
begin
|
begin
|
| Line 114... |
Line 117... |
// o_wb_data <= i_data;
|
// o_wb_data <= i_data;
|
end
|
end
|
|
|
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
|
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
|
begin
|
begin
|
o_wb_cyc_gbl <= 1'b0;
|
r_wb_cyc_gbl <= 1'b0;
|
o_wb_cyc_lcl <= 1'b0;
|
r_wb_cyc_lcl <= 1'b0;
|
cyc <= 1'b0;
|
cyc <= 1'b0;
|
end
|
end
|
end else if (i_pipe_stb) // New memory operation
|
end else if (i_pipe_stb) // New memory operation
|
begin // Grab the wishbone
|
begin // Grab the wishbone
|
o_wb_cyc_lcl <= lcl_stb;
|
r_wb_cyc_lcl <= lcl_stb;
|
o_wb_cyc_gbl <= gbl_stb;
|
r_wb_cyc_gbl <= gbl_stb;
|
o_wb_stb_lcl <= lcl_stb;
|
o_wb_stb_lcl <= lcl_stb;
|
o_wb_stb_gbl <= gbl_stb;
|
o_wb_stb_gbl <= gbl_stb;
|
cyc <= 1'b1;
|
cyc <= 1'b1;
|
// o_wb_addr <= i_addr[(AW-1):0];
|
// o_wb_addr <= i_addr[(AW-1):0];
|
// o_wb_data <= i_data;
|
// o_wb_data <= i_data;
|
| Line 160... |
Line 163... |
if (i_wb_ack)
|
if (i_wb_ack)
|
o_result <= i_wb_data;
|
o_result <= i_wb_data;
|
|
|
assign o_pipe_stalled = (cyc)
|
assign o_pipe_stalled = (cyc)
|
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
|
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
|
|
|
|
generate
|
|
if (IMPLEMENT_LOCK != 0)
|
|
begin
|
|
reg lock_gbl, lock_lcl;
|
|
|
|
initial lock_gbl = 1'b0;
|
|
initial lock_lcl = 1'b0;
|
|
always @(posedge i_clk)
|
|
begin
|
|
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
|
|
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl));
|
|
end
|
|
|
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
|
|
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
|
|
|
|
end else begin
|
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
|
|
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
|
|
end endgenerate
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
