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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Diff between revs 69 and 131
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| Rev 69 |
Rev 131 |
| Line 66... |
Line 66... |
output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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reg cyc;
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reg r_wb_cyc_gbl, r_wb_cyc_lcl;
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reg r_wb_cyc_gbl, r_wb_cyc_lcl;
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reg [3:0] rdaddr, wraddr;
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reg [3:0] rdaddr, wraddr;
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wire [3:0] nxt_rdaddr;
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wire [3:0] nxt_rdaddr;
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reg [(5-1):0] fifo_oreg [0:15];
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reg [(5-1):0] fifo_oreg [0:15];
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initial rdaddr = 0;
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initial rdaddr = 0;
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| Line 86... |
Line 87... |
rdaddr <= 0;
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rdaddr <= 0;
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else if ((i_wb_ack)&&(cyc))
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else if ((i_wb_ack)&&(cyc))
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rdaddr <= rdaddr + 4'h1;
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rdaddr <= rdaddr + 4'h1;
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assign nxt_rdaddr = rdaddr + 4'h1;
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assign nxt_rdaddr = rdaddr + 4'h1;
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reg cyc;
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign gbl_stb = (~lcl_stb);
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assign gbl_stb = (~lcl_stb);
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//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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