| Line 75... |
Line 75... |
fifo_oreg[wraddr] <= i_oreg;
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fifo_oreg[wraddr] <= i_oreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_wb_err))
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if ((i_rst)||(i_wb_err))
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wraddr <= 0;
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wraddr <= 0;
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else if (i_pipe_stb)
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else if (i_pipe_stb)
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wraddr <= wraddr + 1;
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wraddr <= wraddr + 4'h1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_wb_err))
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if ((i_rst)||(i_wb_err))
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rdaddr <= 0;
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rdaddr <= 0;
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else if ((i_wb_ack)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl)))
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else if ((i_wb_ack)&&(cyc))
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rdaddr <= rdaddr + 1;
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rdaddr <= rdaddr + 4'h1;
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assign nxt_rdaddr = rdaddr + 1;
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assign nxt_rdaddr = rdaddr + 4'h1;
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reg cyc;
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wire gbl_stb, lcl_stb;
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wire gbl_stb, lcl_stb;
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assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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assign gbl_stb = ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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assign gbl_stb = (~lcl_stb);
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//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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initial cyc = 0;
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initial o_wb_cyc_lcl = 0;
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initial o_wb_cyc_gbl = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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o_wb_stb_gbl <= 1'b0;
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o_wb_stb_gbl <= 1'b0;
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o_wb_stb_lcl <= 1'b0;
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o_wb_stb_lcl <= 1'b0;
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end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
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cyc <= 1'b0;
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end else if (cyc)
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begin
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begin
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if ((~i_wb_stall)&&(~i_pipe_stb))
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if ((~i_wb_stall)&&(~i_pipe_stb))
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begin
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begin
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o_wb_stb_gbl <= 1'b0;
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o_wb_stb_gbl <= 1'b0;
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o_wb_stb_lcl <= 1'b0;
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o_wb_stb_lcl <= 1'b0;
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end else if ((i_pipe_stb)&&(~i_wb_stall))
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end else if ((i_pipe_stb)&&(~i_wb_stall))
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begin
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begin
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o_wb_addr <= i_addr[(AW-1):0];
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// o_wb_addr <= i_addr[(AW-1):0];
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o_wb_data <= i_data;
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// o_wb_data <= i_data;
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end
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end
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if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
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if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
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begin
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begin
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_gbl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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o_wb_cyc_lcl <= 1'b0;
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cyc <= 1'b0;
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end
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end
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end else if (i_pipe_stb) // New memory operation
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end else if (i_pipe_stb) // New memory operation
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begin // Grab the wishbone
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begin // Grab the wishbone
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o_wb_cyc_lcl <= lcl_stb;
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o_wb_cyc_lcl <= lcl_stb;
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o_wb_cyc_gbl <= gbl_stb;
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o_wb_cyc_gbl <= gbl_stb;
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o_wb_stb_lcl <= lcl_stb;
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o_wb_stb_lcl <= lcl_stb;
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o_wb_stb_gbl <= gbl_stb;
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o_wb_stb_gbl <= gbl_stb;
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cyc <= 1'b1;
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// o_wb_addr <= i_addr[(AW-1):0];
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// o_wb_data <= i_data;
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// o_wb_we <= i_op
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end
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always @(posedge i_clk)
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if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall))
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begin
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o_wb_addr <= i_addr[(AW-1):0];
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o_wb_data <= i_data;
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end else if ((~cyc)&&(i_pipe_stb))
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begin
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o_wb_addr <= i_addr[(AW-1):0];
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o_wb_addr <= i_addr[(AW-1):0];
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o_wb_data <= i_data;
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o_wb_data <= i_data;
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// o_wb_we <= i_op
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_pipe_stb)
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if ((i_pipe_stb)&&(~cyc))
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&&((~i_wb_stall)
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||((~o_wb_cyc_gbl)&&(~o_wb_cyc_lcl))))
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o_wb_we <= i_op;
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o_wb_we <= i_op;
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
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initial o_err = 1'b0;
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initial o_err = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
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o_err <= (cyc)&&(i_wb_err);
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assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
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assign o_busy = cyc;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wreg <= fifo_oreg[rdaddr];
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o_wreg <= fifo_oreg[rdaddr];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_ack)
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if (i_wb_ack)
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o_result <= i_wb_data;
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o_result <= i_wb_data;
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assign o_pipe_stalled = ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
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assign o_pipe_stalled = (cyc)
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&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
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&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
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endmodule
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endmodule
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No newline at end of file
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