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Line 51... |
// Flash requires a minimum of 4 clocks per byte to read, so that would be
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// Flash requires a minimum of 4 clocks per byte to read, so that would be
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// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
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// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
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// mode which this prefetch does not support. In non--pipelined mode, the
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// mode which this prefetch does not support. In non--pipelined mode, the
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// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
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// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
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// or 72 clocks to fetch one instruction.
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// or 72 clocks to fetch one instruction.
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module prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux,
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module prefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stalled_n, i_pc,
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o_i, o_pc, o_aux, o_valid, o_illegal,
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o_i, o_pc, o_valid, o_illegal,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
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parameter ADDRESS_WIDTH=32;
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input i_clk, i_rst, i_ce, i_stalled_n;
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localparam AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_new_pc, i_clear_cache,
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i_stalled_n;
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input [(AW-1):0] i_pc;
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input [(AW-1):0] i_pc;
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input [(AUX_WIDTH-1):0] i_aux;
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output reg [31:0] o_i;
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output reg [31:0] o_i;
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output reg [(AW-1):0] o_pc;
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output wire [(AW-1):0] o_pc;
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output reg [(AUX_WIDTH-1):0] o_aux;
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output reg o_valid;
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output reg o_valid, o_illegal;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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// And return inputs
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// And return inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_illegal;
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assign o_wb_we = 1'b0;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 32'h0000;
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assign o_wb_data = 32'h0000;
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// Let's build it simple and upgrade later: For each instruction
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// Let's build it simple and upgrade later: For each instruction
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// pipeline this, but for now let's just do one at a time.
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// pipeline this, but for now let's just do one at a time.
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initial o_wb_cyc = 1'b0;
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_stb = 1'b0;
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initial o_wb_addr= 0;
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initial o_wb_addr= 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_rst)||(i_wb_ack))
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if ((i_rst)||(i_wb_ack)||(i_wb_err))
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begin
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begin
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o_wb_cyc <= 1'b0;
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
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end else if ((!o_wb_cyc)&&((i_stalled_n)||(!o_valid)))
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begin
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begin // Initiate a bus cycle
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o_wb_cyc <= 1'b1;
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_stb <= 1'b1;
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end else if (o_wb_cyc) // Independent of ce
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end else if (o_wb_cyc) // Independent of ce
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begin
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begin
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if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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if (~i_wb_stall)
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o_wb_stb <= 1'b0;
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o_wb_stb <= 1'b0;
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if (i_wb_ack)
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o_wb_cyc <= 1'b0;
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end
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end
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reg invalid;
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initial invalid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst) // Set the address to guarantee the result is invalid
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if (!o_wb_cyc)
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o_wb_addr <= {(AW){1'b1}};
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invalid <= 1'b0;
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else if ((i_ce)&&(~o_wb_cyc))
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else if ((i_new_pc)||(i_clear_cache))
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o_wb_addr <= i_pc;
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invalid <= (!o_wb_stb);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if (i_new_pc)
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o_aux <= i_aux;
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o_wb_addr <= i_pc;
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else if ((!o_wb_cyc)&&(i_stalled_n)&&(!invalid))
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o_wb_addr <= o_wb_addr + 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if ((o_wb_cyc)&&(i_wb_ack))
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o_i <= i_wb_data;
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o_i <= i_wb_data;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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o_pc <= o_wb_addr;
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initial o_valid = 1'b0;
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initial o_valid = 1'b0;
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initial o_illegal = 1'b0;
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initial o_illegal = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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if (i_rst)
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begin
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o_valid <= 1'b0;
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o_illegal <= 1'b0;
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end else if ((o_wb_cyc)&&(i_wb_ack))
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begin
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begin
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o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err);
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o_valid <= (!i_wb_err)&&(!invalid);
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o_illegal <= (i_wb_err)&&(i_pc == o_wb_addr);
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o_illegal <= ( i_wb_err)&&(!invalid);
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end else if (i_stalled_n)
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end else if ((i_stalled_n)||(i_clear_cache))
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begin
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begin
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o_valid <= 1'b0;
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o_valid <= 1'b0;
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o_illegal <= 1'b0;
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o_illegal <= 1'b0;
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end
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end
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assign o_pc = o_wb_addr;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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