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Line 49... |
// or 72 clocks to fetch one instruction.
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// or 72 clocks to fetch one instruction.
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module prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
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module prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
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o_i, o_pc, o_aux, o_valid, o_illegal,
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o_i, o_pc, o_aux, o_valid, o_illegal,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter AW = 1;
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parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_ce;
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input i_clk, i_rst, i_ce;
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input [31:0] i_pc;
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input [(AW-1):0] i_pc;
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input [(AW-1):0] i_aux;
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input [(AUX_WIDTH-1):0] i_aux;
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output reg [31:0] o_i;
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output reg [31:0] o_i;
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output reg [31:0] o_pc;
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output reg [(AW-1):0] o_pc;
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output reg [(AW-1):0] o_aux;
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output reg [(AUX_WIDTH-1):0] o_aux;
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output wire o_valid, o_illegal;
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output wire o_valid, o_illegal;
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// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_cyc, o_wb_stb;
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output wire o_wb_we;
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output reg [31:0] o_wb_addr;
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output reg [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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// And return inputs
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// And return inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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