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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 105 and 118
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| Rev 105 |
Rev 118 |
| Line 1277... |
Line 1277... |
||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
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||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
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`else
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`else
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assign o_break = (((break_en)||(~op_gie))&&(op_break)
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assign o_break = (((break_en)||(~op_gie))&&(op_break)
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&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
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&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
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&&(~clear_pipeline))
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&&(~clear_pipeline))
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||((~alu_gie)&&(bus_err));
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||((~alu_gie)&&(bus_err))
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||((~alu_gie)&&(div_valid)&&(div_error))
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||((~alu_gie)&&(fpu_valid)&&(fpu_error));
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`endif
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`endif
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// The sleep register. Setting the sleep register causes the CPU to
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// The sleep register. Setting the sleep register causes the CPU to
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// sleep until the next interrupt. Setting the sleep register within
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// sleep until the next interrupt. Setting the sleep register within
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| Line 1630... |
Line 1632... |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
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assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_debug <= {
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o_debug <= {
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pf_pc[3:0], flags,
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i_wb_err, pf_pc[2:0], flags,
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pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
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pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
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op_ce, alu_ce, mem_ce,
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op_ce, alu_ce, mem_ce,
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//
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//
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master_ce, opvalid_alu, opvalid_mem,
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master_ce, opvalid_alu, opvalid_mem,
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//
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//
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