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// Creator:     Dan Gisselquist, Ph.D.

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//              Gisselquist Technology, LLC

//

//

///////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////

//

//

//

//

// This program is free software (firmware): you can redistribute it and/or

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

// your option) any later version.

        input                   i_halt, i_clear_pf_cache;

        input                   i_halt, i_clear_pf_cache;

        input           [4:0]    i_dbg_reg;

        input           [4:0]    i_dbg_reg;

        input                   i_dbg_we;

        input                   i_dbg_we;

        input           [31:0]   i_dbg_data;

        input           [31:0]   i_dbg_data;

        // Debug interface -- outputs

        // Debug interface -- outputs

        output  reg     [31:0]   o_dbg_reg;

        output  reg     [31:0]   o_dbg_reg;

        output  reg     [3:0]    o_dbg_cc;

        output  reg     [3:0]    o_dbg_cc;

        output  wire            o_break;

        output  wire            o_break;

        // Wishbone interface -- outputs

        // Wishbone interface -- outputs

        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;

        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;

        // Condition codes

        // Condition codes

        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z

        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z

        reg     [3:0]    flags, iflags;

        reg     [3:0]    flags, iflags;

        wire    [13:0]   w_uflags, w_iflags;

        wire    [13:0]   w_uflags, w_iflags;

`ifdef  OPT_ILLEGAL_INSTRUCTION

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg             ill_err_u, ill_err_i;

        reg             ill_err_u, ill_err_i;

`else

`else

        wire            ill_err_u, ill_err_i;

        wire            ill_err_u, ill_err_i;

`endif

`endif

        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;

        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;

        reg             opR_wr, opR_cc, opF_wr, op_gie;

        reg             opR_wr, opR_cc, opF_wr, op_gie;

        wire    [13:0]   opFl;

        wire    [13:0]   opFl;

        reg     [5:0]    r_opF;

        reg     [5:0]    r_opF;

        wire    [7:0]    opF;

        wire    [7:0]    opF;

        // Some pipeline control wires

        // Some pipeline control wires

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        reg     opA_alu, opA_mem;

        reg     opA_alu, opA_mem;

        reg     opB_alu, opB_mem;

        reg     opB_alu, opB_mem;

`endif

`endif

`ifdef  OPT_ILLEGAL_INSTRUCTION

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     op_illegal;

        reg     op_illegal;

`endif

`endif

        reg     op_break;

        reg     op_break;

        wire    op_lock;

        wire    op_lock;

        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)

        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)

                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)

                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)

                                &&(set_cond);

                                &&(set_cond);

        //

        //

        //

        //

        //      PIPELINE STAGE #5 :: Write-back

        //      PIPELINE STAGE #5 :: Write-back

        //              Variable declarations

        //              Variable declarations

        //

        //

        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;

        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;

        wire    [4:0]    wr_reg_id;

        wire    [4:0]    wr_reg_id;

        wire    w_switch_to_interrupt, w_release_from_interrupt;

        wire    w_switch_to_interrupt, w_release_from_interrupt;

        reg     [(AW-1):0]       upc, ipc;

        reg     [(AW-1):0]       upc, ipc;

                                // Or if we need to wait on flags to work on the

                                // Or if we need to wait on flags to work on the

                                // CC register

                                // CC register

                                ||(dcdF_stall)

                                ||(dcdF_stall)

                        );

                        );

        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);

        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);

`else

`else

        assign  op_stall = (opvalid)&&(~master_ce);

        assign  op_stall = (opvalid)&&(~master_ce);

        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);

        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);

`endif

`endif

        //

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Calculate stall conditions

        //              Calculate stall conditions

                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                &&(wr_write_cc)) // Case 3

                                &&(wr_write_cc)) // Case 3

                        ||((opvalid)&&(op_lock)&&(op_lock_stall))

                        ||((opvalid)&&(op_lock)&&(op_lock_stall))

                        ||((opvalid)&&(op_break))

                        ||((opvalid)&&(op_break))

                        ||(div_busy)||(fpu_busy);

                        ||(div_busy)||(fpu_busy);

                                &&(~clear_pipeline);

                                &&(~clear_pipeline);

`else

`else

        assign  alu_stall = ((~master_ce)&&(opvalid_alu))

        assign  alu_stall = ((~master_ce)&&(opvalid_alu))

                                ||((opvalid_alu)&&(op_break));

                                ||((opvalid_alu)&&(op_break));

        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);

        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);

                        opB_rd <= dcdB_rd;

                        opB_rd <= dcdB_rd;

                end

                end

`endif

`endif

        always @(posedge i_clk)

        always @(posedge i_clk)

                begin

                begin

                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))

                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))

                        else if (dcdA_pc)

                        else if (dcdA_pc)

                                r_opA <= w_pcA_v;

                                r_opA <= w_pcA_v;

                        else if (dcdA_cc)

                        else if (dcdA_cc)

                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };

                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };

                        else

                        else

                end else

                end else

                begin // We were going to pick these up when they became valid,

                begin // We were going to pick these up when they became valid,

                        // but for some reason we're stuck here as they became

                        // but for some reason we're stuck here as they became

                        // valid.  Pick them up now anyway

                        // valid.  Pick them up now anyway

                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))

                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))

                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))

                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))

`endif

`endif

                end

                end

        wire    [31:0]   w_opBnI, w_pcB_v;

        wire    [31:0]   w_opBnI, w_pcB_v;

        generate

        generate

        else

        else

                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;

                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;

        endgenerate

        endgenerate

        assign  w_opBnI = (~dcdB_rd) ? 32'h00

        assign  w_opBnI = (~dcdB_rd) ? 32'h00

                : ((dcdB_pc) ? w_pcB_v

                : ((dcdB_pc) ? w_pcB_v

                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],

                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],

                        (dcdB[4])?w_uflags:w_iflags}

                        (dcdB[4])?w_uflags:w_iflags}

                : w_opB)));

                : w_opB)));

        always @(posedge i_clk)

        always @(posedge i_clk)

                        r_opB <= w_opBnI + dcdI;

                        r_opB <= w_opBnI + dcdI;

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))

                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))

`endif

`endif

        // The logic here has become more complex than it should be, no thanks

        // The logic here has become more complex than it should be, no thanks

        // to Xilinx's Vivado trying to help.  The conditions are supposed to

        // to Xilinx's Vivado trying to help.  The conditions are supposed to

        // be two sets of four bits: the top bits specify what bits matter, the

        // be two sets of four bits: the top bits specify what bits matter, the

        // conditions checking those bits.  Therefore, Vivado complains that

        // conditions checking those bits.  Therefore, Vivado complains that

        // these two bits are redundant.  Hence the convoluted expression

        // these two bits are redundant.  Hence the convoluted expression

        // below, arriving at what we finally want in the (now wire net)

        // below, arriving at what we finally want in the (now wire net)

        // opF.

        // opF.

        always @(posedge i_clk)

        always @(posedge i_clk)

                begin // Set the flag condition codes, bit order is [3:0]=VNCZ

                begin // Set the flag condition codes, bit order is [3:0]=VNCZ

                        case(dcdF[2:0])

                        case(dcdF[2:0])

                        3'h0:   r_opF <= 6'h00; // Always

                        3'h0:   r_opF <= 6'h00; // Always

`ifdef  OPT_NEW_INSTRUCTION_SET

`ifdef  OPT_NEW_INSTRUCTION_SET

                        // These were remapped as part of the new instruction

                        // These were remapped as part of the new instruction

                        opvalid_alu <= (dcdALU)&&(w_opvalid);

                        opvalid_alu <= (dcdALU)&&(w_opvalid);

                        opvalid_mem <= (dcdM)&&(w_opvalid);

                        opvalid_mem <= (dcdM)&&(w_opvalid);

                        opvalid_div <= (dcdDV)&&(w_opvalid);

                        opvalid_div <= (dcdDV)&&(w_opvalid);

                        opvalid_fpu <= (dcdFP)&&(w_opvalid);

                        opvalid_fpu <= (dcdFP)&&(w_opvalid);

`endif

`endif

                begin

                begin

                        opvalid     <= 1'b0;

                        opvalid     <= 1'b0;

                        opvalid_alu <= 1'b0;

                        opvalid_alu <= 1'b0;

                        opvalid_mem <= 1'b0;

                        opvalid_mem <= 1'b0;

                        opvalid_div <= 1'b0;

                        opvalid_div <= 1'b0;

                assign  op_lock_stall = r_op_lock_stall;

                assign  op_lock_stall = r_op_lock_stall;

                initial r_op_lock = 1'b0;

                initial r_op_lock = 1'b0;

                always @(posedge i_clk)

                always @(posedge i_clk)

                                r_op_lock <= 1'b0;

                                r_op_lock <= 1'b0;

                        else if (op_ce)

                        else if (op_ce)

                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);

                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);

                assign  op_lock = r_op_lock;

                assign  op_lock = r_op_lock;

                                &&(~dcd_early_branch)&&(~dcd_illegal);

                                &&(~dcd_early_branch)&&(~dcd_illegal);

                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);

                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);

                end

                end

        always @(posedge i_clk)

        always @(posedge i_clk)

                begin

                begin

                        opn    <= dcdOp;        // Which ALU operation?

                        opn    <= dcdOp;        // Which ALU operation?

                        // opM  <= dcdM;        // Is this a memory operation?

                        // opM  <= dcdM;        // Is this a memory operation?

                        // What register will these results be written into?

                        // What register will these results be written into?

                        opR    <= dcdR;

                        opR    <= dcdR;

        reg     r_op_phase;

        reg     r_op_phase;

        initial r_op_phase = 1'b0;

        initial r_op_phase = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((i_rst)||(clear_pipeline))

                if ((i_rst)||(clear_pipeline))

                        r_op_phase <= 1'b0;

                        r_op_phase <= 1'b0;

                        r_op_phase <= dcd_phase;

                        r_op_phase <= dcd_phase;

        assign  op_phase = r_op_phase;

        assign  op_phase = r_op_phase;

`else

`else

        assign  op_phase = 1'b0;

        assign  op_phase = 1'b0;

`endif

`endif

        // We'll create a flag here to start our coordination.  Once we

        // We'll create a flag here to start our coordination.  Once we

        // define this flag to something other than just plain zero, then

        // define this flag to something other than just plain zero, then

        // the stalls will already be in place.

        // the stalls will already be in place.

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))

        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))

`else

`else

        assign  opA = r_opA;

        assign  opA = r_opA;

`endif

`endif

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        assign  dcdA_stall = 1'b0;

        assign  dcdA_stall = 1'b0;

`endif

`endif

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))

        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))

`else

`else

        assign  opB = r_opB;

        assign  opB = r_opB;

`endif

`endif

`ifdef  OPT_PIPELINED

`ifdef  OPT_PIPELINED

        reg     r_alu_phase;

        reg     r_alu_phase;

        initial r_alu_phase = 1'b0;

        initial r_alu_phase = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (i_rst)

                if (i_rst)

                        r_alu_phase <= 1'b0;

                        r_alu_phase <= 1'b0;

                        r_alu_phase <= op_phase;

                        r_alu_phase <= op_phase;

        assign  alu_phase = r_alu_phase;

        assign  alu_phase = r_alu_phase;

`else

`else

        assign  alu_phase = 1'b0;

        assign  alu_phase = 1'b0;

`endif

`endif

        always @(posedge i_clk)

        always @(posedge i_clk)

                        alu_reg <= opR;

                        alu_reg <= opR;

                else if ((i_halt)&&(i_dbg_we))

                else if ((i_halt)&&(i_dbg_we))

                        alu_reg <= i_dbg_reg;

                        alu_reg <= i_dbg_reg;

        //

        //

        // DEBUG Register write access starts here

        // DEBUG Register write access starts here

        //

        //

        reg             dbgv;

        reg             dbgv;

        initial dbgv = 1'b0;

        initial dbgv = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

        reg     [31:0]   dbg_val;

        reg     [31:0]   dbg_val;

        always @(posedge i_clk)

        always @(posedge i_clk)

                dbg_val <= i_dbg_data;

                dbg_val <= i_dbg_data;

        always @(posedge i_clk)

        always @(posedge i_clk)

                        alu_gie  <= op_gie;

                        alu_gie  <= op_gie;

        always @(posedge i_clk)

        always @(posedge i_clk)

                                &&(~mem_stalled)))

                                &&(~mem_stalled)))

                        alu_pc  <= op_pc;

                        alu_pc  <= op_pc;

`ifdef  OPT_ILLEGAL_INSTRUCTION

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     r_alu_illegal;

        reg     r_alu_illegal;

        initial r_alu_pc_valid = 1'b0;

        initial r_alu_pc_valid = 1'b0;

        initial mem_pc_valid = 1'b0;

        initial mem_pc_valid = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (i_rst)

                if (i_rst)

                        r_alu_pc_valid <= 1'b0;

                        r_alu_pc_valid <= 1'b0;

                        r_alu_pc_valid <= 1'b1;

                        r_alu_pc_valid <= 1'b1;

                        r_alu_pc_valid <= 1'b0;

                        r_alu_pc_valid <= 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (i_rst)

                if (i_rst)

                        mem_pc_valid <= 1'b0;

                        mem_pc_valid <= 1'b0;

                else

                else

                        mem_pc_valid <= (mem_ce);

                        mem_pc_valid <= (mem_ce);

        //      Note that the flags needed to be checked before issuing the

        //      Note that the flags needed to be checked before issuing the

        //      bus instruction, so they don't need to be checked here.

        //      bus instruction, so they don't need to be checked here.

        //      Further, alu_wr includes (set_cond), so we don't need to

        //      Further, alu_wr includes (set_cond), so we don't need to

        //      check for that here either.

        //      check for that here either.

`ifdef  OPT_ILLEGAL_INSTRUCTION

`ifdef  OPT_ILLEGAL_INSTRUCTION

`endif

`endif

        // Which register shall be written?

        // Which register shall be written?

        //      COULD SIMPLIFY THIS: by adding three bits to these registers,

        //      COULD SIMPLIFY THIS: by adding three bits to these registers,

        //              One or PC, one for CC, and one for GIE match

        //              One or PC, one for CC, and one for GIE match

        //      Note that the alu_reg is the register to write on a divide or

        //      Note that the alu_reg is the register to write on a divide or

        //      FPU operation.

        //      FPU operation.

        // Are we writing to the CC register?

        // Are we writing to the CC register?

        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);

        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);

        // Are we writing to the PC?

        // Are we writing to the PC?

        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);

        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);

        // What value to write?

        // What value to write?

                                :((div_valid|fpu_valid))

                                :((div_valid|fpu_valid))

                                        ? ((div_valid) ? div_result:fpu_result)

                                        ? ((div_valid) ? div_result:fpu_result)

                                :((dbgv) ? dbg_val : alu_result));

                                :((dbgv) ? dbg_val : alu_result));

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (wr_reg_ce)

                if (wr_reg_ce)

        //

        //

        // Write back to the condition codes/flags register ...

        // Write back to the condition codes/flags register ...

        // When shall we write to our flags register?  alF_wr already

        // When shall we write to our flags register?  alF_wr already

        // includes the set condition ...

        // includes the set condition ...

        // What value to write?

        // What value to write?

        always @(posedge i_clk)

        always @(posedge i_clk)

                // If explicitly writing the register itself

                // If explicitly writing the register itself

                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))

                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))

                // Otherwise if we're setting the flags from an ALU operation

                // Otherwise if we're setting the flags from an ALU operation

                else if ((wr_flags_ce)&&(alu_gie))

                else if ((wr_flags_ce)&&(alu_gie))

                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags

                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags

                                : alu_flags);

                                : alu_flags);

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))

                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))

                else if ((wr_flags_ce)&&(~alu_gie))

                else if ((wr_flags_ce)&&(~alu_gie))

                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags

                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags

                                : alu_flags);

                                : alu_flags);

        // The 'break' enable  bit.  This bit can only be set from supervisor

        // The 'break' enable  bit.  This bit can only be set from supervisor

        initial break_en = 1'b0;

        initial break_en = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((i_rst)||(i_halt))

                if ((i_rst)||(i_halt))

                        break_en <= 1'b0;

                        break_en <= 1'b0;

                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))

                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))

`ifdef  OPT_ILLEGAL_INSTRUCTION

`ifdef  OPT_ILLEGAL_INSTRUCTION

        assign  o_break = ((break_en)||(~op_gie))&&(op_break)

        assign  o_break = ((break_en)||(~op_gie))&&(op_break)

                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)

                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)

                                &&(~div_busy)&&(~fpu_busy)

                                &&(~div_busy)&&(~fpu_busy)

                                &&(~clear_pipeline)

                                &&(~clear_pipeline)

                        ||((~alu_gie)&&(bus_err))

                        ||((~alu_gie)&&(bus_err))

                        ||((~alu_gie)&&(div_valid)&&(div_error))

                        ||((~alu_gie)&&(div_valid)&&(div_error))

                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))

                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))

                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));

                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));

`else

`else

        assign  o_break = (((break_en)||(~op_gie))&&(op_break)

        assign  o_break = (((break_en)||(~op_gie))&&(op_break)

                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)

                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)

                                &&(~clear_pipeline))

                                &&(~clear_pipeline))

                        ||((~alu_gie)&&(bus_err))

                        ||((~alu_gie)&&(bus_err))

                        ||((~alu_gie)&&(div_valid)&&(div_error))

                        ||((~alu_gie)&&(div_valid)&&(div_error))

                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));

                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));

`endif

`endif

                        // In supervisor mode, we have no protections.  The

                        // In supervisor mode, we have no protections.  The

                        // supervisor can set the sleep bit however he wants.

                        // supervisor can set the sleep bit however he wants.

                        // Well ... not quite.  Switching to user mode and

                        // Well ... not quite.  Switching to user mode and

                        // sleep mode shouold only be possible if the interrupt

                        // sleep mode shouold only be possible if the interrupt

                        // flag isn't set.

                        // flag isn't set.

                        //              don't set the sleep bit

                        //              don't set the sleep bit

                        //      otherwise however it would o.w. be set

                        //      otherwise however it would o.w. be set

                        // In user mode, however, you can only set the sleep

                        // In user mode, however, you can only set the sleep

                        // mode while remaining in user mode.  You can't switch

                        // mode while remaining in user mode.  You can't switch

                        // to sleep mode *and* supervisor mode at the same

                        // to sleep mode *and* supervisor mode at the same

                        // time, lest you halt the CPU.

                        // time, lest you halt the CPU.

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((i_rst)||(w_switch_to_interrupt))

                if ((i_rst)||(w_switch_to_interrupt))

                        step <= 1'b0;

                        step <= 1'b0;

                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))

                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))

                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))

                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))

                        step <= 1'b0;

                        step <= 1'b0;

        // The GIE register.  Only interrupts can disable the interrupt register

        // The GIE register.  Only interrupts can disable the interrupt register

        assign  w_switch_to_interrupt = (gie)&&(

        assign  w_switch_to_interrupt = (gie)&&(

                        // Same thing on a floating point error.

                        // Same thing on a floating point error.

                        ||((fpu_valid)&&(fpu_error))

                        ||((fpu_valid)&&(fpu_error))

                        //      

                        //      

                        ||(bus_err)

                        ||(bus_err)

                        // If we write to the CC register

                        // If we write to the CC register

                                &&(wr_reg_id[4])&&(wr_write_cc))

                                &&(wr_reg_id[4])&&(wr_write_cc))

                        );

                        );

        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)

        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)

                        // Then if we write the CC register

                        // Then if we write the CC register

                                &&(~wr_reg_id[4])&&(wr_write_cc))

                                &&(~wr_reg_id[4])&&(wr_write_cc))

                        );

                        );

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (i_rst)

                if (i_rst)

                        gie <= 1'b0;

                        gie <= 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if (i_rst)

                if (i_rst)

                        trap <= 1'b0;

                        trap <= 1'b0;

                else if (w_release_from_interrupt)