| Line 104... |
Line 104... |
// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// We can either pipeline our fetches, or issue one fetch at a time. Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2. However, the area cost may be worth it. Consider:
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//
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// Slice LUTs ZipSystem ZipCPU
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// Single Fetching 2521 1734
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// Pipelined fetching 2796 2046
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//
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// `define SINGLE_FETCH
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//
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//
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//
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`define CPU_CC_REG 4'he
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`define CPU_CC_REG 4'he
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`define CPU_PC_REG 4'hf
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`define CPU_PC_REG 4'hf
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`define CPU_TRAP_BIT 9
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`define CPU_TRAP_BIT 9
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`define CPU_BREAK_BIT 7
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`define CPU_BREAK_BIT 7
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`define CPU_STEP_BIT 6
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`define CPU_STEP_BIT 6
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`define CPU_GIE_BIT 5
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`define CPU_GIE_BIT 5
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`define CPU_SLEEP_BIT 4
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`define CPU_SLEEP_BIT 4
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// Compile time defines
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// `define SINGLE_FETCH
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`define NG_CONDITIONAL_FLAGS
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`define NG_PRECLEAR_BUS // 0.61 w/ or w/o
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// `define NG_BRANCH_DELAY_SLOT
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`define NG_ILLEGAL_INSTRUCTION
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`define NG_EARLY_BRANCHING // 0.60 w/, 0.61 w/o ????
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module zipcpu(i_clk, i_rst, i_interrupt,
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module zipcpu(i_clk, i_rst, i_interrupt,
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// Debug interface
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// Debug interface
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_break,
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o_break,
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// CPU interface to the wishbone bus
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// CPU interface to the wishbone bus
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_err,
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// Accounting/CPU usage interface
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// Accounting/CPU usage interface
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o_op_stall, o_pf_stall, o_i_count);
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o_op_stall, o_pf_stall, o_i_count);
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parameter RESET_ADDRESS=32'h0100000;
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parameter RESET_ADDRESS=32'h0100000;
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input i_clk, i_rst, i_interrupt;
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input i_clk, i_rst, i_interrupt;
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// Debug interface -- inputs
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// Debug interface -- inputs
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| Line 134... |
Line 158... |
output reg o_dbg_stall;
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output reg o_dbg_stall;
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output reg [31:0] o_dbg_reg;
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output reg [31:0] o_dbg_reg;
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output reg [1:0] o_dbg_cc;
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output reg [1:0] o_dbg_cc;
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output wire o_break;
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output wire o_break;
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// Wishbone interface -- outputs
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// Wishbone interface -- outputs
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_gbl_cyc, o_wb_gbl_stb;
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output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire [31:0] o_wb_addr, o_wb_data;
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output wire [31:0] o_wb_addr, o_wb_data;
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// Wishbone interface -- inputs
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// Wishbone interface -- inputs
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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// Accounting outputs ... to help us count stalls and usage
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// Accounting outputs ... to help us count stalls and usage
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output wire o_op_stall;
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output wire o_op_stall;
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output wire o_pf_stall;
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output wire o_pf_stall;
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output wire o_i_count;
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output wire o_i_count;
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| Line 150... |
Line 176... |
// Registers
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// Registers
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reg [31:0] regset [0:31];
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reg [31:0] regset [0:31];
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|
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// Condition codes
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// Condition codes
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reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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wire [9:0] w_uflags, w_iflags;
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wire [10:0] w_uflags, w_iflags;
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reg trap, break_en, step, gie, sleep;
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reg trap, break_en, step, gie, sleep;
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`ifdef NG_ILLEGAL_INSTRUCTION
|
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reg ill_err;
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`endif
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reg bus_err_flag;
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|
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// The master chip enable
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// The master chip enable
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wire master_ce;
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wire master_ce;
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|
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//
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//
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| Line 164... |
Line 194... |
// Variable declarations
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// Variable declarations
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//
|
//
|
reg [31:0] pf_pc;
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reg [31:0] pf_pc;
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reg new_pc, op_break;
|
reg new_pc, op_break;
|
wire clear_pipeline;
|
wire clear_pipeline;
|
assign clear_pipeline = new_pc || i_clear_pf_cache || op_break;
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assign clear_pipeline = new_pc || i_clear_pf_cache; // || op_break;
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|
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wire dcd_stalled;
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wire dcd_stalled;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] pf_addr, pf_data;
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wire [31:0] instruction, instruction_pc;
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wire [31:0] instruction, instruction_pc;
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wire pf_valid, instruction_gie;
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wire pf_valid, instruction_gie, pf_illegal;
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|
|
//
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//
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//
|
//
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// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
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// Variable declarations
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// Variable declarations
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| Line 190... |
Line 220... |
dcdM, dcdF_wr, dcd_gie, dcd_break;
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dcdM, dcdF_wr, dcd_gie, dcd_break;
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reg [31:0] dcd_pc;
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reg [31:0] dcd_pc;
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reg [23:0] r_dcdI;
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reg [23:0] r_dcdI;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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|
|
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`ifdef NG_PRECLEAR_BUS
|
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reg dcd_clear_bus;
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`endif
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`ifdef NG_ILLEGAL_INSTRUCTION
|
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reg dcd_illegal;
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`endif
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`ifdef NG_EARLY_BRANCHING
|
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reg dcd_early_branch_stb, dcd_early_branch;
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reg [31:0] dcd_branch_pc;
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`else
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wire dcd_early_branch_stb, dcd_early_branch;
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wire [31:0] dcd_branch_pc;
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`endif
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|
|
|
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//
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//
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
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// PIPELINE STAGE #3 :: Read Operands
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| Line 208... |
Line 251... |
reg [31:0] r_opA, r_opB, op_pc;
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reg [31:0] r_opA, r_opB, op_pc;
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wire [31:0] w_opA, w_opB;
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wire [31:0] w_opA, w_opB;
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wire [31:0] opA_nowait, opB_nowait, opA, opB;
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wire [31:0] opA_nowait, opB_nowait, opA, opB;
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reg opR_wr, opR_cc, opF_wr, op_gie,
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reg opR_wr, opR_cc, opF_wr, op_gie,
|
opA_rd, opB_rd;
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opA_rd, opB_rd;
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wire [9:0] opFl;
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wire [10:0] opFl;
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reg [6:0] r_opF;
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reg [6:0] r_opF;
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wire [8:0] opF;
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wire [8:0] opF;
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wire op_ce;
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wire op_ce;
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`ifdef NG_PRECLEAR_BUS
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reg op_clear_bus;
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`endif
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`ifdef NG_ILLEGAL_INSTRUCTION
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reg op_illegal;
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`endif
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//
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//
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//
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//
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// PIPELINE STAGE #4 :: ALU / Memory
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// PIPELINE STAGE #4 :: ALU / Memory
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| Line 229... |
Line 277... |
wire [31:0] alu_result;
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wire [31:0] alu_result;
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wire [3:0] alu_flags;
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wire [3:0] alu_flags;
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wire alu_valid;
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wire alu_valid;
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wire set_cond;
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wire set_cond;
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reg alu_wr, alF_wr, alu_gie;
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reg alu_wr, alF_wr, alu_gie;
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`ifdef NG_ILLEGAL_INSTRUCTION
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reg alu_illegal;
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`endif
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wire mem_ce, mem_stalled;
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wire mem_ce, mem_stalled;
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wire mem_valid, mem_ack, mem_stall,
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wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
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mem_cyc, mem_stb, mem_we;
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mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
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wire [4:0] mem_wreg;
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wire [4:0] mem_wreg;
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|
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wire mem_busy, mem_rdbusy;
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wire mem_busy, mem_rdbusy;
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wire [31:0] mem_addr, mem_data, mem_result;
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wire [31:0] mem_addr, mem_data, mem_result;
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| Line 272... |
Line 323... |
// Calculate stall conditions
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// Calculate stall conditions
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assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
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assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
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assign dcd_stalled = (dcdvalid)&&(
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assign dcd_stalled = (dcdvalid)&&(
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(op_stall)
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(op_stall)
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||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
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||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
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||((opvalid)&&((op_wr_pc)||(opR_cc))));
|
`ifndef NG_BRANCH_DELAY_SLOT
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||((opvalid_mem)&&(op_wr_pc))
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`endif
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||((opvalid_mem)&&(opR_cc)));
|
//
|
//
|
// PIPELINE STAGE #3 :: Read Operands
|
// PIPELINE STAGE #3 :: Read Operands
|
// Calculate stall conditions
|
// Calculate stall conditions
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assign op_stall = ((mem_stalled)&&(opvalid_mem))
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assign op_stall = ((mem_stalled)&&(opvalid_mem))
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||((alu_stall)&&(opvalid_alu));
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||((alu_stall)&&(opvalid_alu));
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assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
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assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
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|
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//
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//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu))
|
//
|
|
// 1. Basic stall is if the previous stage is valid and the next is
|
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// busy.
|
|
// 2. Also stall if the prior stage is valid and the master clock enable
|
|
// is de-selected
|
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// 3. Next case: Stall if we want to start a memory operation and the
|
|
// prior operation will write either the PC or CC registers.
|
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
|
// through the ALU. Break instructions are not allowed through
|
|
// the ALU.
|
|
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
|
|
`ifdef BEFORE
|
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
&&(wr_write_pc)||(wr_write_cc));
|
&&((wr_write_pc)||(wr_write_cc)) // Case 3
|
|
`else
|
|
||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
|
&&((wr_write_pc)||(wr_write_cc))) // Case 3
|
|
`endif
|
|
||((opvalid)&&(op_break)); // Case 4
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
//
|
//
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
(~master_ce)
|
(~master_ce)
|
| Line 309... |
Line 379... |
wire pf_ce;
|
wire pf_ce;
|
|
|
assign pf_ce = (~dcd_stalled);
|
assign pf_ce = (~dcd_stalled);
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
|
instruction, instruction_pc, instruction_gie,
|
instruction, instruction_pc, instruction_gie,
|
pf_valid,
|
pf_valid, pf_illegal,
|
pf_cyc, pf_stb, pf_we, pf_addr,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_data,
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
pf_ack, pf_stall, i_wb_data);
|
|
`else // Pipe fetch
|
`else // Pipe fetch
|
pipefetch #(RESET_ADDRESS)
|
pipefetch #(RESET_ADDRESS)
|
pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc,
|
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
|
|
i_clear_pf_cache, ~dcd_stalled,
|
|
(new_pc)?pf_pc:dcd_branch_pc,
|
instruction, instruction_pc, pf_valid,
|
instruction, instruction_pc, pf_valid,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
pf_ack, pf_stall, i_wb_data,
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
mem_cyc);
|
`ifdef NG_PRECLEAR_BUS
|
|
((dcd_clear_bus)&&(dcdvalid))
|
|
||((op_clear_bus)&&(opvalid))
|
|
||
|
|
`endif
|
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
|
pf_illegal);
|
assign instruction_gie = gie;
|
assign instruction_gie = gie;
|
`endif
|
`endif
|
|
|
|
initial dcdvalid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
dcdvalid <= 1'b0;
|
dcdvalid <= 1'b0;
|
else if (dcd_ce)
|
else if (dcd_ce)
|
dcdvalid <= (~clear_pipeline);
|
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
|
else if ((~dcd_stalled)||(clear_pipeline))
|
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
|
dcdvalid <= 1'b0;
|
dcdvalid <= 1'b0;
|
|
|
|
`ifdef NG_EARLY_BRANCHING
|
|
always @(posedge i_clk)
|
|
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG))
|
|
begin
|
|
dcd_early_branch <= 1'b0;
|
|
// First case, a move to PC instruction
|
|
if ((instruction[31:28] == 4'h2)
|
|
&&((instruction_gie)
|
|
||((~instruction[20])&&(~instruction[15])))
|
|
&&(instruction[23:21]==3'h0))
|
|
begin
|
|
dcd_early_branch_stb <= 1'b1;
|
|
dcd_early_branch <= 1'b1;
|
|
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
|
|
|
|
end else // Next case, an Add Imm -> PC instruction
|
|
if ((instruction[31:28] == 4'ha) // Add
|
|
&&(~instruction[20]) // Immediate
|
|
&&(instruction[23:21]==3'h0)) // Always
|
|
begin
|
|
dcd_early_branch_stb <= 1'b1;
|
|
dcd_early_branch <= 1'b1;
|
|
// r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
|
|
end else // Next case: load Immediate to PC
|
|
if (instruction[31:28] == 4'h3)
|
|
begin
|
|
dcd_early_branch_stb <= 1'b1;
|
|
dcd_early_branch <= 1'b1;
|
|
// r_dcdI <= { instruction[23:0] };
|
|
end
|
|
end else
|
|
begin
|
|
if (dcd_ce) dcd_early_branch <= 1'b0;
|
|
dcd_early_branch_stb <= 1'b0;
|
|
end
|
|
always @(posedge i_clk)
|
|
if (dcd_ce)
|
|
begin
|
|
if (instruction[31]) // Add
|
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(12){instruction[19]}}, instruction[19:0] };
|
|
else if (~instruction[28]) // 4'h2 = MOV
|
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(17){instruction[14]}}, instruction[14:0] };
|
|
else // if (instruction[28]) // 4'h3 = LDI
|
|
dcd_branch_pc <= instruction_pc+32'h01+{ {(8){instruction[23]}}, instruction[23:0] };
|
|
end
|
|
`else // NG_EARLY_BRANCHING
|
|
assign dcd_early_branch_stb = 1'b0;
|
|
assign dcd_early_branch = 1'b0;
|
|
assign dcd_branch_pc = 32'h00;
|
|
`endif // NG_EARLY_BRANCHING
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dcd_ce)
|
if (dcd_ce)
|
begin
|
begin
|
dcd_pc <= instruction_pc+1;
|
dcd_pc <= instruction_pc+1;
|
|
|
| Line 347... |
Line 476... |
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
|
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
|
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdM <= 1'b0;
|
dcdM <= 1'b0;
|
|
`ifdef NG_CONDITIONAL_FLAGS
|
|
dcdF_wr <= (instruction[23:21]==3'h0);
|
|
`else
|
dcdF_wr <= 1'b1;
|
dcdF_wr <= 1'b1;
|
|
`endif
|
|
`ifdef NG_PRECLEAR_BUS
|
|
dcd_clear_bus <= 1'b0;
|
|
`endif
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
dcd_illegal <= pf_illegal;
|
|
`endif
|
|
|
// Set the condition under which we do this operation
|
// Set the condition under which we do this operation
|
// The top four bits are a mask, the bottom four the
|
// The top four bits are a mask, the bottom four the
|
// value the flags must equal once anded with the mask
|
// value the flags must equal once anded with the mask
|
dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
|
dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
|
| Line 376... |
Line 515... |
dcdF_wr <= 1'b0; // Don't write flags
|
dcdF_wr <= 1'b0; // Don't write flags
|
dcdF <= 4'h8; // This is unconditional
|
dcdF <= 4'h8; // This is unconditional
|
dcdOp <= 4'h2;
|
dcdOp <= 4'h2;
|
end
|
end
|
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
|
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
|
|
`ifdef NG_CONDITIONAL_FLAGS
|
|
// Don't write flags except for multiplies
|
|
// and then only if they are unconditional
|
|
dcdF_wr <= ((instruction[27:25] != 3'h7)
|
|
&&(instruction[23:21]==3'h0));
|
|
`else
|
// Don't write flags except for multiplies
|
// Don't write flags except for multiplies
|
dcdF_wr <= (instruction[27:25] != 3'h7);
|
dcdF_wr <= (instruction[27:25] != 3'h7);
|
|
`endif
|
r_dcdI <= { 8'h00, instruction[15:0] };
|
r_dcdI <= { 8'h00, instruction[15:0] };
|
if (instruction[27:24] == 4'he)
|
if (instruction[27:24] == 4'he)
|
begin
|
begin
|
// NOOP instruction
|
// NOOP instruction
|
dcdA_wr <= 1'b0;
|
dcdA_wr <= 1'b0;
|
dcdA_rd <= 1'b0;
|
dcdA_rd <= 1'b0;
|
dcdB_rd <= 1'b0;
|
dcdB_rd <= 1'b0;
|
dcdOp <= 4'h2;
|
dcdOp <= 4'h2;
|
|
// Might also be a break. Big
|
|
// instruction set hole here.
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
|
|
`endif
|
end else if (instruction[27:24] == 4'hf)
|
end else if (instruction[27:24] == 4'hf)
|
begin // Load partial immediate(s)
|
begin // Load partial immediate(s)
|
dcdA_wr <= 1'b1;
|
dcdA_wr <= 1'b1;
|
dcdA_rd <= 1'b1;
|
dcdA_rd <= 1'b1;
|
dcdB_rd <= 1'b0;
|
dcdB_rd <= 1'b0;
|
| Line 412... |
Line 563... |
if (instruction[20])
|
if (instruction[20])
|
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
|
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
|
else
|
else
|
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
|
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
|
dcdM <= 1'b1; // Memory operation
|
dcdM <= 1'b1; // Memory operation
|
|
`ifdef NG_PRECLEAR_BUS
|
|
dcd_clear_bus <= (instruction[23:21]==3'h0);
|
|
`endif
|
end
|
end
|
default: begin
|
default: begin
|
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
|
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
|
dcdA_rd <= 1'b1;
|
dcdA_rd <= 1'b1;
|
dcdB_rd <= instruction[20];
|
dcdB_rd <= instruction[20];
|
| Line 430... |
Line 584... |
dcd_gie <= instruction_gie;
|
dcd_gie <= instruction_gie;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dcd_ce)
|
if (dcd_ce)
|
dcd_break <= (instruction[31:0] == 32'h4e000001);
|
dcd_break <= (instruction[31:0] == 32'h4e000001);
|
else
|
else if ((clear_pipeline)||(~dcdvalid))
|
dcd_break <= 1'b0;
|
dcd_break <= 1'b0;
|
|
|
|
|
//
|
//
|
//
|
//
|
| Line 451... |
Line 605... |
else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
|
else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
|
r_opA <= dcd_pc;
|
r_opA <= dcd_pc;
|
else if (dcdA_pc)
|
else if (dcdA_pc)
|
r_opA <= upc;
|
r_opA <= upc;
|
else if (dcdA_cc)
|
else if (dcdA_cc)
|
r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags };
|
r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
|
else
|
else
|
r_opA <= w_opA;
|
r_opA <= w_opA;
|
end
|
end
|
wire [31:0] dcdI;
|
wire [31:0] dcdI, w_opBnI;
|
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
|
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
|
|
assign w_opBnI = (~dcdB_rd) ? 32'h00
|
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
|
|
: (((dcdB_pc)&&(dcdB[4] == dcd_gie)) ? dcd_pc
|
|
: ((dcdB_pc) ? upc
|
|
: ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
|
|
: regset[dcdB]))));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce) // &&(dcdvalid))
|
if (op_ce) // &&(dcdvalid))
|
begin
|
r_opB <= w_opBnI + dcdI;
|
if (~dcdB_rd)
|
|
r_opB <= dcdI;
|
|
else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
|
|
r_opB <= wr_reg_vl + dcdI;
|
|
else if ((dcdB_pc)&&(dcdB[4] == dcd_gie))
|
|
r_opB <= dcd_pc + dcdI;
|
|
else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user
|
|
r_opB <= upc + dcdI;
|
|
else if (dcdB_cc)
|
|
r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI;
|
|
else
|
|
r_opB <= regset[dcdB] + dcdI;
|
|
end
|
|
|
|
// The logic here has become more complex than it should be, no thanks
|
// The logic here has become more complex than it should be, no thanks
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
// be two sets of four bits: the top bits specify what bits matter, the
|
// be two sets of four bits: the top bits specify what bits matter, the
|
// bottom specify what those top bits must equal. However, two of
|
// bottom specify what those top bits must equal. However, two of
|
| Line 485... |
Line 632... |
// these two bits are redundant. Hence the convoluted expression
|
// these two bits are redundant. Hence the convoluted expression
|
// below, arriving at what we finally want in the (now wire net)
|
// below, arriving at what we finally want in the (now wire net)
|
// opF.
|
// opF.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin // Set the flag condition codes
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
case(dcdF[2:0])
|
case(dcdF[2:0])
|
3'h0: r_opF <= 7'h80; // Always
|
3'h0: r_opF <= 7'h80; // Always
|
3'h1: r_opF <= 7'h11; // Z
|
3'h1: r_opF <= 7'h11; // Z
|
3'h2: r_opF <= 7'h10; // NE
|
3'h2: r_opF <= 7'h10; // NE
|
3'h3: r_opF <= 7'h20; // GE (!N)
|
3'h3: r_opF <= 7'h20; // GE (!N)
|
3'h4: r_opF <= 7'h30; // GT (!N&!Z)
|
3'h4: r_opF <= 7'h30; // GT (!N&!Z)
|
3'h5: r_opF <= 7'h24; // LT
|
3'h5: r_opF <= 7'h24; // LT
|
3'h6: r_opF <= 7'h02; // C
|
3'h6: r_opF <= 7'h02; // C
|
3'h7: r_opF <= 7'h08; // V
|
3'h7: r_opF <= 7'h08; // V
|
endcase
|
endcase
|
end
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
assign opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
assign opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
|
|
|
initial opvalid = 1'b0;
|
|
initial opvalid_alu = 1'b0;
|
|
initial opvalid_mem = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
begin
|
begin
|
opvalid <= 1'b0;
|
opvalid <= 1'b0;
|
opvalid_alu <= 1'b0;
|
opvalid_alu <= 1'b0;
|
| Line 516... |
Line 666... |
// move forward, and get a stall cycle inserted.
|
// move forward, and get a stall cycle inserted.
|
// Hence, the test on dcd_stalled here. If we must
|
// Hence, the test on dcd_stalled here. If we must
|
// wait until our operands are valid, then we aren't
|
// wait until our operands are valid, then we aren't
|
// valid yet until then.
|
// valid yet until then.
|
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
|
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
|
`else
|
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
|
|
`endif
|
end else if ((~op_stall)||(clear_pipeline))
|
end else if ((~op_stall)||(clear_pipeline))
|
begin
|
begin
|
opvalid <= 1'b0;
|
opvalid <= 1'b0;
|
opvalid_alu <= 1'b0;
|
opvalid_alu <= 1'b0;
|
opvalid_mem <= 1'b0;
|
opvalid_mem <= 1'b0;
|
| Line 541... |
Line 696... |
if (i_rst) op_break <= 1'b0;
|
if (i_rst) op_break <= 1'b0;
|
else if (op_ce) op_break <= (dcd_break);
|
else if (op_ce) op_break <= (dcd_break);
|
else if ((clear_pipeline)||(~opvalid))
|
else if ((clear_pipeline)||(~opvalid))
|
op_break <= 1'b0;
|
op_break <= 1'b0;
|
|
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
always @(posedge i_clk)
|
|
if(op_ce)
|
|
op_illegal <= dcd_illegal;
|
|
`endif
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
begin
|
begin
|
opn <= dcdOp; // Which ALU operation?
|
opn <= dcdOp; // Which ALU operation?
|
// opM <= dcdM; // Is this a memory operation?
|
// opM <= dcdM; // Is this a memory operation?
|
|
`ifdef NG_EARLY_BRANCH
|
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
|
|
opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
|
|
`else
|
// Will we write the flags/CC Register with our result?
|
// Will we write the flags/CC Register with our result?
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
|
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
|
// Will we be writing our results into a register?
|
// Will we be writing our results into a register?
|
opR_wr <= dcdA_wr;
|
opR_wr <= dcdA_wr;
|
|
`endif
|
// What register will these results be written into?
|
// What register will these results be written into?
|
opR <= dcdA;
|
opR <= dcdA;
|
opR_cc <= (dcdA_wr)&&(dcdA_cc);
|
opR_cc <= (dcdA_wr)&&(dcdA_cc);
|
// User level (1), vs supervisor (0)/interrupts disabled
|
// User level (1), vs supervisor (0)/interrupts disabled
|
op_gie <= dcd_gie;
|
op_gie <= dcd_gie;
|
| Line 565... |
Line 731... |
// use that value.
|
// use that value.
|
opA_rd <= dcdA_rd;
|
opA_rd <= dcdA_rd;
|
opB_rd <= dcdB_rd;
|
opB_rd <= dcdB_rd;
|
op_pc <= dcd_pc;
|
op_pc <= dcd_pc;
|
//
|
//
|
|
`ifdef NG_EARLY_BRANCHING
|
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
|
|
`else
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
|
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
|
|
`endif
|
|
|
|
`ifdef NG_PRECLEAR_BUS
|
|
op_clear_bus <= dcd_clear_bus;
|
|
`endif
|
end
|
end
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
|
|
// This is tricky. First, the PC and Flags registers aren't kept in
|
// This is tricky. First, the PC and Flags registers aren't kept in
|
// register set but in special registers of their own. So step one
|
// register set but in special registers of their own. So step one
|
| Line 581... |
Line 755... |
// The alternative approach would be to define some sort of
|
// The alternative approach would be to define some sort of
|
// op_stall wire, which would stall any upstream stage.
|
// op_stall wire, which would stall any upstream stage.
|
// We'll create a flag here to start our coordination. Once we
|
// We'll create a flag here to start our coordination. Once we
|
// define this flag to something other than just plain zero, then
|
// define this flag to something other than just plain zero, then
|
// the stalls will already be in place.
|
// the stalls will already be in place.
|
`define DONT_STALL_ON_OPA
|
|
`ifdef DONT_STALL_ON_OPA
|
|
reg opA_alu;
|
reg opA_alu;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
|
opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
|
assign opA = (opA_alu) ? alu_result : r_opA;
|
assign opA = (opA_alu) ? alu_result : r_opA;
|
`else
|
|
assign opA = r_opA;
|
|
`endif
|
|
|
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
|
`define DONT_STALL_ON_OPA
|
|
`ifdef DONT_STALL_ON_OPA
|
|
// Skip the requirement on writing back opA
|
// Skip the requirement on writing back opA
|
// Stall on memory, since we'll always need to stall for a
|
// Stall on memory, since we'll always need to stall for a
|
// memory access anyway
|
// memory access anyway
|
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
|
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
|
((opvalid_alu)&&(opF_wr)&&(dcdA_cc))||
|
((opvalid_alu)&&(opF_wr)&&(dcdA_cc))||
|
`else
|
|
((opvalid)&&(opR_wr)&&(opR == dcdA))||
|
|
`endif
|
|
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
|
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
|
`define DONT_STALL_ON_OPB
|
|
`ifdef DONT_STALL_ON_OPB
|
|
reg opB_alu;
|
reg opB_alu;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
|
assign opB = (opB_alu) ? alu_result : r_opB;
|
assign opB = (opB_alu) ? alu_result : r_opB;
|
`else
|
|
assign opB = r_opB;
|
|
`endif
|
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
((opvalid)&&(opR_wr)&&(opR == dcdB)
|
&&((opvalid_mem)||(dcdI != 0)))
|
&&((opvalid_mem)||(dcdI != 0)))
|
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
|
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
|
`ifdef DONT_STALL_ON_OPB
|
|
`endif
|
|
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
|
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
|
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
|
&&(opvalid)&&(opR_cc);
|
&&(opvalid)&&(opR_cc);
|
//
|
//
|
//
|
//
|
| Line 664... |
Line 822... |
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
|
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
|
&&((opvalid_alu)||(~mem_stalled));
|
&&((opvalid_alu)||(~mem_stalled));
|
|
|
memops domem(i_clk, i_rst, mem_ce,
|
memops domem(i_clk, i_rst, mem_ce,
|
(opn[0]), opB, opA, opR,
|
(opn[0]), opB, opA, opR,
|
mem_busy, mem_valid, mem_wreg, mem_result,
|
mem_busy, mem_valid, bus_err, mem_wreg, mem_result,
|
mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_ack, mem_stall, i_wb_data);
|
mem_stb_gbl, mem_stb_lcl,
|
assign mem_rdbusy = ((mem_cyc)&&(~mem_we));
|
mem_we, mem_addr, mem_data,
|
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
|
assign mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
wbarbiter #(32,32) pformem(i_clk, i_rst,
|
wbdblpriarb #(32,32) pformem(i_clk, i_rst,
|
|
// Memory access to the arbiter, priority position
|
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
|
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
|
// Prefetch access to the arbiter
|
// Prefetch access to the arbiter
|
pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
|
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
|
// Memory access to the arbiter
|
pf_ack, pf_stall, pf_err,
|
mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
|
|
// Common wires, in and out, of the arbiter
|
// Common wires, in and out, of the arbiter
|
o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
i_wb_stall);
|
o_wb_we, o_wb_addr, o_wb_data,
|
|
i_wb_ack, i_wb_stall, i_wb_err);
|
|
|
//
|
//
|
//
|
//
|
// PIPELINE STAGE #5 :: Write-back results
|
// PIPELINE STAGE #5 :: Write-back results
|
//
|
//
|
| Line 698... |
Line 861... |
// When shall we write back? On one of two conditions
|
// When shall we write back? On one of two conditions
|
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
assign wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
|
`else
|
|
assign wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
|
`endif
|
// Which register shall be written?
|
// Which register shall be written?
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
| Line 717... |
Line 884... |
|
|
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alF_wr already
|
// includes the set condition ...
|
// includes the set condition ...
|
assign wr_flags_ce = (alF_wr)&&(alu_valid);
|
assign wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
|
assign w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
assign w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
|
`else
|
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
|
`endif
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// If explicitly writing the register itself
|
// If explicitly writing the register itself
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
flags <= wr_reg_vl[3:0];
|
flags <= wr_reg_vl[3:0];
|
| Line 765... |
Line 937... |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
break_en <= i_dbg_data[`CPU_BREAK_BIT];
|
break_en <= i_dbg_data[`CPU_BREAK_BIT];
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
|
&&(~clear_pipeline)
|
|
||((~alu_gie)&&(bus_err))
|
|
||((~alu_gie)&&(alu_valid)&&(alu_illegal));
|
|
`else
|
|
assign o_break = (((break_en)||(~op_gie))&&(op_break)
|
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
|
&&(~clear_pipeline))
|
|
||((~alu_gie)&&(bus_err))
|
|
`endif
|
|
|
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
// The sleep register. Setting the sleep register causes the CPU to
|
// sleep until the next interrupt. Setting the sleep register within
|
// sleep until the next interrupt. Setting the sleep register within
|
// interrupt mode causes the processor to halt until a reset. This is
|
// interrupt mode causes the processor to halt until a reset. This is
|
| Line 809... |
Line 992... |
// On interrupt (obviously)
|
// On interrupt (obviously)
|
(i_interrupt)
|
(i_interrupt)
|
// If we are stepping the CPU
|
// If we are stepping the CPU
|
||((master_ce)&&(alu_pc_valid)&&(step))
|
||((master_ce)&&(alu_pc_valid)&&(step))
|
// If we encounter a break instruction, if the break
|
// If we encounter a break instruction, if the break
|
// enable isn't not set.
|
// enable isn't set.
|
||((master_ce)&&(op_break)&&(~break_en))
|
||((master_ce)&&(op_break)&&(~break_en))
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
// On an illegal instruction
|
|
||((alu_valid)&&(alu_illegal))
|
|
`endif
|
// If we write to the CC register
|
// If we write to the CC register
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
// Or if, in debug mode, we write to the CC register
|
// Or if, in debug mode, we write to the CC register
|
||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
|
||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
|
| Line 847... |
Line 1034... |
&&(~i_dbg_data[`CPU_GIE_BIT]))
|
&&(~i_dbg_data[`CPU_GIE_BIT]))
|
trap <= i_dbg_data[`CPU_TRAP_BIT];
|
trap <= i_dbg_data[`CPU_TRAP_BIT];
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
|
|
|
`ifdef NG_ILLEGAL_INSTRUCTION
|
|
initial ill_err = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
ill_err <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
ill_err <= 1'b0;
|
|
else if ((alu_valid)&&(alu_illegal)&&(gie))
|
|
ill_err <= 1'b1;
|
|
`endif
|
|
initial bus_err_flag = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
bus_err_flag <= 1'b0;
|
|
else if (w_release_from_interrupt)
|
|
bus_err_flag <= 1'b0;
|
|
else if ((bus_err)&&(alu_gie))
|
|
bus_err_flag <= 1'b1;
|
|
|
//
|
//
|
// Write backs to the PC register, and general increments of it
|
// Write backs to the PC register, and general increments of it
|
// We support two: upc and ipc. If the instruction is normal,
|
// We support two: upc and ipc. If the instruction is normal,
|
// we increment upc, if interrupt level we increment ipc. If
|
// we increment upc, if interrupt level we increment ipc. If
|
// the instruction writes the PC, we write whichever PC is appropriate.
|
// the instruction writes the PC, we write whichever PC is appropriate.
|
| Line 860... |
Line 1066... |
// it? Do we clear both? What if a gie instruction tries to clear
|
// it? Do we clear both? What if a gie instruction tries to clear
|
// a non-gie instruction?
|
// a non-gie instruction?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= wr_reg_vl;
|
upc <= wr_reg_vl;
|
else if ((alu_gie)&&(alu_pc_valid))
|
else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
upc <= alu_pc;
|
upc <= alu_pc;
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
|
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
|
upc <= i_dbg_data;
|
upc <= i_dbg_data;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ipc <= RESET_ADDRESS;
|
ipc <= RESET_ADDRESS;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
ipc <= wr_reg_vl;
|
ipc <= wr_reg_vl;
|
else if ((~alu_gie)&&(alu_pc_valid))
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
ipc <= alu_pc;
|
ipc <= alu_pc;
|
else if ((i_halt)&&(i_dbg_we)
|
else if ((i_halt)&&(i_dbg_we)
|
&&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
|
&&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
|
ipc <= i_dbg_data;
|
ipc <= i_dbg_data;
|
|
|
| Line 916... |
Line 1122... |
begin
|
begin
|
o_dbg_reg <= regset[i_dbg_reg];
|
o_dbg_reg <= regset[i_dbg_reg];
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_cc <= { gie, sleep };
|
o_dbg_cc <= { gie, sleep };
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_stall <= (i_halt)&&(
|
o_dbg_stall <= (i_halt)&&(
|
(pf_cyc)||(mem_cyc)||(mem_busy)
|
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
|
||((~opvalid)&&(~i_rst))
|
||((~opvalid)&&(~i_rst))
|
||((~dcdvalid)&&(~i_rst)));
|
||((~dcdvalid)&&(~i_rst)));
|
|
|
//
|
//
|
//
|
//
|
