| Line 202... |
Line 202... |
reg [1:0] opA_cc, opB_cc;
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reg [1:0] opA_cc, opB_cc;
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reg [31:0] r_opA, r_opB, op_pc;
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reg [31:0] r_opA, r_opB, op_pc;
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wire [31:0] opA_nowait, opB_nowait, opA, opB;
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wire [31:0] opA_nowait, opB_nowait, opA, opB;
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reg opR_wr, opM, opF_wr, op_gie,
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reg opR_wr, opM, opF_wr, op_gie,
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opA_rd, opB_rd;
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opA_rd, opB_rd;
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reg [7:0] opFl;
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wire [7:0] opFl;
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// reg [6:0] r_opF;
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reg [6:0] r_opF;
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wire [8:0] opF;
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wire [8:0] opF;
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wire op_ce;
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wire op_ce;
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| Line 305... |
Line 305... |
pf_valid,
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pf_valid,
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pf_cyc, pf_stb, pf_we, pf_addr,
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pf_cyc, pf_stb, pf_we, pf_addr,
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pf_data,
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pf_data,
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pf_ack, pf_stall, i_wb_data);
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pf_ack, pf_stall, i_wb_data);
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`else // Pipe fetch
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`else // Pipe fetch
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pipefetch pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
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pipefetch #(RESET_ADDRESS)
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pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
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instruction, instruction_pc, pf_valid,
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instruction, instruction_pc, pf_valid,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
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pf_ack, pf_stall, i_wb_data);
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pf_ack, pf_stall, i_wb_data,
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mem_cyc);
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assign instruction_gie = gie;
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assign instruction_gie = gie;
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`endif
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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| Line 455... |
Line 457... |
// conditions check whether bits are on, and those are the only two
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// conditions check whether bits are on, and those are the only two
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// conditions checking those bits. Therefore, Vivado complains that
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// conditions checking those bits. Therefore, Vivado complains that
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// these two bits are redundant. Hence the convoluted expression
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// these two bits are redundant. Hence the convoluted expression
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// below, arriving at what we finally want in the (now wire net)
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// below, arriving at what we finally want in the (now wire net)
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// opF.
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// opF.
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`define NEWCODE
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`ifdef NEWCODE
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`ifdef NEWCODE
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (op_ce)
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if (op_ce)
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begin // Set the flag condition codes
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begin // Set the flag condition codes
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case(dcdF[2:0])
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case(dcdF[2:0])
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| Line 577... |
Line 580... |
&&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
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&&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
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||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
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||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
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assign opA = { r_opA[31:8], ((opA_cc[0]) ?
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assign opA = { r_opA[31:8], ((opA_cc[0]) ?
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((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
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((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
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assign opB = { r_opB[31:8], ((opB_cc[0]) ?
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assign opB = { r_opB[31:8], ((opB_cc[0]) ?
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((opA_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
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((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
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//
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//
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//
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//
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// PIPELINE STAGE #4 :: Apply Instruction
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// PIPELINE STAGE #4 :: Apply Instruction
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//
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//
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