| Line 63... |
Line 63... |
//
|
//
|
// Slice LUTs ZipSystem ZipCPU
|
// Slice LUTs ZipSystem ZipCPU
|
// Single Fetching 2521 1734
|
// Single Fetching 2521 1734
|
// Pipelined fetching 2796 2046
|
// Pipelined fetching 2796 2046
|
//
|
//
|
// `define OPT_SINGLE_FETCH
|
|
//
|
|
//
|
//
|
//
|
//
|
`define CPU_CC_REG 4'he
|
`define CPU_CC_REG 4'he
|
`define CPU_PC_REG 4'hf
|
`define CPU_PC_REG 4'hf
|
|
`define CPU_BUSERR_BIT 10
|
`define CPU_TRAP_BIT 9
|
`define CPU_TRAP_BIT 9
|
|
`define CPU_ILL_BIT 8
|
`define CPU_BREAK_BIT 7
|
`define CPU_BREAK_BIT 7
|
`define CPU_STEP_BIT 6
|
`define CPU_STEP_BIT 6
|
`define CPU_GIE_BIT 5
|
`define CPU_GIE_BIT 5
|
`define CPU_SLEEP_BIT 4
|
`define CPU_SLEEP_BIT 4
|
// Compile time defines
|
// Compile time defines
|
//
|
//
|
`include "cpudefs.v"
|
`include "cpudefs.v"
|
//
|
//
|
|
//
|
|
//
|
|
// `define DEBUG_SCOPE
|
|
//
|
|
//
|
|
//
|
module zipcpu(i_clk, i_rst, i_interrupt,
|
module zipcpu(i_clk, i_rst, i_interrupt,
|
// Debug interface
|
// Debug interface
|
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
|
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
|
o_dbg_stall, o_dbg_reg, o_dbg_cc,
|
o_dbg_stall, o_dbg_reg, o_dbg_cc,
|
o_break,
|
o_break,
|
| Line 90... |
Line 96... |
o_wb_lcl_cyc, o_wb_lcl_stb,
|
o_wb_lcl_cyc, o_wb_lcl_stb,
|
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_err,
|
i_wb_err,
|
// Accounting/CPU usage interface
|
// Accounting/CPU usage interface
|
o_op_stall, o_pf_stall, o_i_count,
|
o_op_stall, o_pf_stall, o_i_count
|
//
|
`ifdef DEBUG_SCOPE
|
o_debug);
|
, o_debug
|
|
`endif
|
|
);
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
|
LGICACHE=6, AW=ADDRESS_WIDTH;
|
LGICACHE=6, AW=ADDRESS_WIDTH;
|
`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
|
parameter IMPLEMENT_MPY = 1;
|
parameter IMPLEMENT_MPY = 1;
|
`else
|
`else
|
| Line 125... |
Line 133... |
// Accounting outputs ... to help us count stalls and usage
|
// Accounting outputs ... to help us count stalls and usage
|
output wire o_op_stall;
|
output wire o_op_stall;
|
output wire o_pf_stall;
|
output wire o_pf_stall;
|
output wire o_i_count;
|
output wire o_i_count;
|
//
|
//
|
|
`ifdef DEBUG_SCOPE
|
output reg [31:0] o_debug;
|
output reg [31:0] o_debug;
|
|
`endif
|
|
|
|
|
// Registers
|
// Registers
|
//
|
//
|
// The distributed RAM style comment is necessary on the
|
// The distributed RAM style comment is necessary on the
|
| Line 146... |
Line 156... |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
|
reg [3:0] flags, iflags;
|
reg [3:0] flags, iflags;
|
wire [10:0] w_uflags, w_iflags;
|
wire [10:0] w_uflags, w_iflags;
|
reg trap, break_en, step, gie, sleep;
|
reg trap, break_en, step, gie, sleep;
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg ill_err;
|
reg ill_err_u, ill_err_i;
|
`else
|
`else
|
wire ill_err;
|
wire ill_err_u, ill_err_i;
|
`endif
|
`endif
|
reg bus_err_flag;
|
reg ibus_err_flag, ubus_err_flag;
|
|
|
// The master chip enable
|
// The master chip enable
|
wire master_ce;
|
wire master_ce;
|
|
|
//
|
//
|
| Line 299... |
Line 309... |
|
|
|
|
//
|
//
|
// PIPELINE STAGE #1 :: Prefetch
|
// PIPELINE STAGE #1 :: Prefetch
|
// Calculate stall conditions
|
// Calculate stall conditions
|
|
//
|
|
// These are calculated externally, within the prefetch module.
|
|
//
|
|
|
//
|
//
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// PIPELINE STAGE #2 :: Instruction Decode
|
// Calculate stall conditions
|
// Calculate stall conditions
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
|
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
|
| Line 322... |
Line 335... |
//
|
//
|
// ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
|
// ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
|
// Stall if we are going into memory with an operation
|
// Stall if we are going into memory with an operation
|
// that cannot be pipelined, and the memory is
|
// that cannot be pipelined, and the memory is
|
// already busy
|
// already busy
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
//
|
//
|
// Stall if we are going into memory with a pipeable
|
// Stall if we are going into memory with a pipeable
|
// operation, but the memory unit declares it is
|
// operation, but the memory unit declares it is
|
// not going to accept any more pipeline operations
|
// not going to accept any more pipeline operations
|
||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
|
|
`else
|
|
||((opvalid_mem)&&(mem_busy))
|
|
`endif
|
|
);
|
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
|
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
|
|
|
//
|
//
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// PIPELINE STAGE #4 :: ALU / Memory
|
// Calculate stall conditions
|
// Calculate stall conditions
|
| Line 350... |
Line 368... |
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
&&(wr_write_cc)) // Case 3
|
&&(wr_write_cc)) // Case 3
|
||((opvalid_alu)&&(op_break)); // Case 3
|
||((opvalid_alu)&&(op_break)); // Case 3
|
assign alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
assign alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
|
//
|
//
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
|
|
//
|
|
// Note: if you change the conditions for mem_ce, you must also change
|
|
// alu_pc_valid.
|
|
//
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
&&(set_cond)&&(~mem_stalled);
|
&&(set_cond)&&(~mem_stalled);
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
assign mem_stalled = (~master_ce)||((opvalid_mem)&&(
|
assign mem_stalled = (~master_ce)||((opvalid_mem)&&(
|
(mem_pipe_stalled)
|
(mem_pipe_stalled)
|
||((~op_pipe)&&(mem_busy))
|
||((~op_pipe)&&(mem_busy))
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
// Or CC register, since that can change the
|
// Or CC register, since that can change the
|
// PC as well
|
// PC as well
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
&&((wr_write_pc)||(wr_write_cc)))));
|
&&((wr_write_pc)||(wr_write_cc)))));
|
`else
|
`else
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
|
|
|
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
(~master_ce)
|
(~master_ce)
|
// Stall waiting for flags to be valid
|
// Stall waiting for flags to be valid
|
// Or waiting for a write to the PC register
|
// Or waiting for a write to the PC register
|
// Or CC register, since that can change the
|
// Or CC register, since that can change the
|
| Line 424... |
Line 445... |
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
|
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
|
begin
|
begin
|
dcd_early_branch <= 1'b0;
|
dcd_early_branch <= 1'b0;
|
// First case, a move to PC instruction
|
// First case, a move to PC instruction
|
if ((instruction[31:28] == 4'h2)
|
if ((instruction[31:28] == 4'h2)
|
|
// Offsets of the PC register *only*
|
|
&&(instruction[19:16] == `CPU_PC_REG)
|
&&((instruction_gie)
|
&&((instruction_gie)
|
||((~instruction[20])&&(~instruction[15])))
|
||((~instruction[20])&&(~instruction[15])))
|
&&(instruction[23:21]==3'h0))
|
&&(instruction[23:21]==3'h0)) // Unconditional
|
begin
|
begin
|
dcd_early_branch_stb <= 1'b1;
|
dcd_early_branch_stb <= 1'b1;
|
dcd_early_branch <= 1'b1;
|
dcd_early_branch <= 1'b1;
|
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
|
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
|
|
|
| Line 510... |
Line 533... |
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
|
dcdM <= 1'b0;
|
dcdM <= 1'b0;
|
`ifdef OPT_CONDITIONAL_FLAGS
|
`ifdef OPT_CONDITIONAL_FLAGS
|
dcdF_wr <= (instruction[23:21]==3'h0);
|
// Don't change the flags on conditional instructions,
|
|
// UNLESS: the conditional instruction was a CMP
|
|
// or TST instruction.
|
|
dcdF_wr <= ((instruction[23:21]==3'h0)
|
|
||(instruction[31:29] == 3'h0));
|
`else
|
`else
|
dcdF_wr <= 1'b1;
|
dcdF_wr <= 1'b1;
|
`endif
|
`endif
|
`ifdef OPT_PRECLEAR_BUS
|
`ifdef OPT_PRECLEAR_BUS
|
dcd_clear_bus <= 1'b0;
|
dcd_clear_bus <= 1'b0;
|
| Line 664... |
Line 691... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce)
|
if (op_ce)
|
op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
|
op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
|
&&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
|
&&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
|
&&(dcdB == op_B) // Same address register
|
&&(dcdB == op_B) // Same address register
|
&&(dcdF[2:0] == opF_cp) // Same condition
|
&&((dcdF[2:0] == opF_cp) // Same condition
|
|
||(opF_cp == 3'h0)) // or no prev condition
|
&&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
|
&&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce) // &&(dcdvalid))
|
if (op_ce) // &&(dcdvalid))
|
r_opI <= r_dcdI;
|
r_opI <= r_dcdI;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 705... |
Line 733... |
`ifdef OPT_SINGLE_CYCLE
|
`ifdef OPT_SINGLE_CYCLE
|
end else if (opvalid)
|
end else if (opvalid)
|
begin // We were going to pick these up when they became valid,
|
begin // We were going to pick these up when they became valid,
|
// but for some reason we're stuck here as they became
|
// but for some reason we're stuck here as they became
|
// valid. Pick them up now anyway
|
// valid. Pick them up now anyway
|
if (((opA_alu)&&(alu_valid)&&(alu_wr))||((opA_mem)&&(mem_valid)))
|
if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
|
r_opA <= wr_reg_vl;
|
r_opA <= wr_reg_vl;
|
`endif
|
`endif
|
end
|
end
|
|
|
wire [31:0] dcdI, w_opBnI, w_pcB_v;
|
wire [31:0] dcdI, w_opBnI, w_pcB_v;
|
| Line 730... |
Line 758... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (op_ce) // &&(dcdvalid))
|
if (op_ce) // &&(dcdvalid))
|
r_opB <= w_opBnI + dcdI;
|
r_opB <= w_opBnI + dcdI;
|
`ifdef OPT_SINGLE_CYCLE
|
`ifdef OPT_SINGLE_CYCLE
|
else if ((opvalid)&&(
|
else if ((opvalid)&&(
|
((opB_alu)&&(alu_valid)&&(alu_wr))
|
((opB_alu)&&(alu_wr))
|
||((opB_mem)&&(mem_valid))))
|
||((opB_mem)&&(mem_valid))))
|
r_opB <= wr_reg_vl;
|
r_opB <= wr_reg_vl;
|
`endif
|
`endif
|
|
|
// The logic here has become more complex than it should be, no thanks
|
// The logic here has become more complex than it should be, no thanks
|
| Line 887... |
Line 915... |
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (mem_ce)
|
if (mem_ce)
|
mem_last_reg <= opR;
|
mem_last_reg <= opR;
|
`ifdef OPT_SINGLE_CYCLE
|
`ifdef OPT_SINGLE_CYCLE
|
assign opA = ((opA_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
|
assign opA = ((opA_alu)&&(alu_wr)) ? alu_result
|
: ( ((opA_mem)&&(mem_valid))?mem_result
|
: ( ((opA_mem)&&(mem_valid))?mem_result
|
: r_opA );
|
: r_opA );
|
`else
|
`else
|
assign opA = r_opA;
|
assign opA = r_opA;
|
`endif
|
`endif
|
| Line 919... |
Line 947... |
((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
|
((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
|
||((~opvalid)&&(mem_busy)&&(~mem_we)
|
||((~opvalid)&&(mem_busy)&&(~mem_we)
|
&&(mem_last_reg == dcdB)));
|
&&(mem_last_reg == dcdB)));
|
else if ((opvalid)&&(opB_mem)&&(mem_valid))
|
else if ((opvalid)&&(opB_mem)&&(mem_valid))
|
opB_mem <= 1'b0;
|
opB_mem <= 1'b0;
|
assign opB = ((opB_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
|
assign opB = ((opB_alu)&&(alu_wr)) ? alu_result
|
: ( ((opB_mem)&&(mem_valid))?mem_result
|
: ( ((opB_mem)&&(mem_valid))?mem_result
|
: r_opB );
|
: r_opB );
|
`else
|
`else
|
assign opB = r_opB;
|
assign opB = r_opB;
|
`endif
|
`endif
|
| Line 974... |
Line 1002... |
begin
|
begin
|
alu_wr <= 1'b0;
|
alu_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
end else if (alu_ce)
|
end else if (alu_ce)
|
begin
|
begin
|
alu_reg <= opR;
|
// alu_reg <= opR;
|
alu_wr <= (opR_wr)&&(set_cond);
|
alu_wr <= (opR_wr)&&(set_cond);
|
alF_wr <= (opF_wr)&&(set_cond);
|
alF_wr <= (opF_wr)&&(set_cond);
|
end else begin
|
end else begin
|
// These are strobe signals, so clear them if not
|
// These are strobe signals, so clear them if not
|
// set for any particular clock
|
// set for any particular clock
|
alu_wr <= 1'b0;
|
alu_wr <= (i_halt)&&(i_dbg_we);
|
alF_wr <= 1'b0;
|
alF_wr <= 1'b0;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
|
if (alu_ce)
|
|
alu_reg <= opR;
|
|
else if ((i_halt)&&(i_dbg_we))
|
|
alu_reg <= i_dbg_reg;
|
|
reg [31:0] dbg_val;
|
|
reg dbgv;
|
|
always @(posedge i_clk)
|
|
dbg_val <= i_dbg_data;
|
|
initial dbgv = 1'b0;
|
|
always @(posedge i_clk)
|
|
dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
|
|
always @(posedge i_clk)
|
if ((alu_ce)||(mem_ce))
|
if ((alu_ce)||(mem_ce))
|
alu_gie <= op_gie;
|
alu_gie <= op_gie;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||(mem_ce))
|
if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
|
&&(~mem_stalled)))
|
alu_pc <= op_pc;
|
alu_pc <= op_pc;
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
reg r_alu_illegal;
|
reg r_alu_illegal;
|
initial r_alu_illegal = 0;
|
initial r_alu_illegal = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((alu_ce)||(mem_ce))
|
if ((alu_ce)||(mem_ce))
|
r_alu_illegal <= op_illegal;
|
r_alu_illegal <= op_illegal;
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
`endif
|
`endif
|
|
|
|
// This _almost_ is equal to (alu_ce)||(mem_ce). The only
|
|
// problem is that mem_ce is gated by the set_cond, and
|
|
// the PC will be valid independent of the set condition. Hence, this
|
|
// equals (alu_ce)||(everything in mem_ce but the set condition)
|
initial alu_pc_valid = 1'b0;
|
initial alu_pc_valid = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
|
alu_pc_valid <= ((alu_ce)
|
&&((opvalid_alu)||(~mem_stalled));
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
|
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
pipemem #(AW) domem(i_clk, i_rst, mem_ce,
|
pipemem #(AW) domem(i_clk, i_rst, mem_ce,
|
(opn[0]), opB, opA, opR,
|
(opn[0]), opB, opA, opR,
|
mem_busy, mem_pipe_stalled,
|
mem_busy, mem_pipe_stalled,
|
| Line 1023... |
Line 1069... |
mem_cyc_gbl, mem_cyc_lcl,
|
mem_cyc_gbl, mem_cyc_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_stb_gbl, mem_stb_lcl,
|
mem_we, mem_addr, mem_data,
|
mem_we, mem_addr, mem_data,
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
`endif // PIPELINED_BUS_ACCESS
|
`endif // PIPELINED_BUS_ACCESS
|
assign mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
// Either the prefetch or the instruction gets the memory bus, but
|
// never both.
|
// never both.
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
// Memory access to the arbiter, priority position
|
// Memory access to the arbiter, priority position
|
| Line 1058... |
Line 1104... |
// Note that the flags needed to be checked before issuing the
|
// Note that the flags needed to be checked before issuing the
|
// bus instruction, so they don't need to be checked here.
|
// bus instruction, so they don't need to be checked here.
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// Further, alu_wr includes (set_cond), so we don't need to
|
// check for that here either.
|
// check for that here either.
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
|
`else
|
`else
|
assign wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
|
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
|
`endif
|
`endif
|
// Which register shall be written?
|
// Which register shall be written?
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
// One or PC, one for CC, and one for GIE match
|
// One or PC, one for CC, and one for GIE match
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
|
// Are we writing to the CC register?
|
// Are we writing to the CC register?
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
// Are we writing to the PC?
|
// Are we writing to the PC?
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
// What value to write?
|
// What value to write?
|
assign wr_reg_vl = (alu_wr)?alu_result:mem_result;
|
assign wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wr_reg_ce)
|
if (wr_reg_ce)
|
regset[wr_reg_id] <= wr_reg_vl;
|
regset[wr_reg_id] <= wr_reg_vl;
|
else if ((i_halt)&&(i_dbg_we))
|
|
regset[i_dbg_reg] <= i_dbg_data[31:0];
|
|
|
|
//
|
//
|
// Write back to the condition codes/flags register ...
|
// Write back to the condition codes/flags register ...
|
// When shall we write to our flags register? alF_wr already
|
// When shall we write to our flags register? alF_wr already
|
// includes the set condition ...
|
// includes the set condition ...
|
assign wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
|
assign wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { bus_err_flag, trap, ill_err,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
assign w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
`else
|
`else
|
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
assign w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
`endif
|
`endif
|
// What value to write?
|
// What value to write?
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// If explicitly writing the register itself
|
// If explicitly writing the register itself
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
|
flags <= wr_reg_vl[3:0];
|
flags <= wr_reg_vl[3:0];
|
// Otherwise if we're setting the flags from an ALU operation
|
// Otherwise if we're setting the flags from an ALU operation
|
else if ((wr_flags_ce)&&(alu_gie))
|
else if ((wr_flags_ce)&&(alu_gie))
|
flags <= alu_flags;
|
flags <= alu_flags;
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
|
|
flags <= i_dbg_data[3:0];
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
iflags <= wr_reg_vl[3:0];
|
iflags <= wr_reg_vl[3:0];
|
else if ((wr_flags_ce)&&(~alu_gie))
|
else if ((wr_flags_ce)&&(~alu_gie))
|
iflags <= alu_flags;
|
iflags <= alu_flags;
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
|
iflags <= i_dbg_data[3:0];
|
|
|
|
// The 'break' enable bit. This bit can only be set from supervisor
|
// The 'break' enable bit. This bit can only be set from supervisor
|
// mode. It control what the CPU does upon encountering a break
|
// mode. It control what the CPU does upon encountering a break
|
// instruction.
|
// instruction.
|
//
|
//
|
| Line 1132... |
Line 1170... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(i_halt))
|
if ((i_rst)||(i_halt))
|
break_en <= 1'b0;
|
break_en <= 1'b0;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
break_en <= wr_reg_vl[`CPU_BREAK_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
|
|
break_en <= i_dbg_data[`CPU_BREAK_BIT];
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
assign o_break = ((break_en)||(~op_gie))&&(op_break)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
|
&&(~clear_pipeline)
|
&&(~clear_pipeline)
|
||((~alu_gie)&&(bus_err))
|
||((~alu_gie)&&(bus_err))
|
| Line 1168... |
Line 1203... |
// In user mode, however, you can only set the sleep
|
// In user mode, however, you can only set the sleep
|
// mode while remaining in user mode. You can't switch
|
// mode while remaining in user mode. You can't switch
|
// to sleep mode *and* supervisor mode at the same
|
// to sleep mode *and* supervisor mode at the same
|
// time, lest you halt the CPU.
|
// time, lest you halt the CPU.
|
sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
|
sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
|
|
sleep <= i_dbg_data[`CPU_SLEEP_BIT];
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((i_rst)||(w_switch_to_interrupt))
|
if ((i_rst)||(w_switch_to_interrupt))
|
step <= 1'b0;
|
step <= 1'b0;
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
|
step <= wr_reg_vl[`CPU_STEP_BIT];
|
step <= wr_reg_vl[`CPU_STEP_BIT];
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
|
|
step <= i_dbg_data[`CPU_STEP_BIT];
|
|
else if ((alu_pc_valid)&&(step)&&(gie))
|
else if ((alu_pc_valid)&&(step)&&(gie))
|
step <= 1'b0;
|
step <= 1'b0;
|
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
// The GIE register. Only interrupts can disable the interrupt register
|
assign w_switch_to_interrupt = (gie)&&(
|
assign w_switch_to_interrupt = (gie)&&(
|
| Line 1199... |
Line 1228... |
||((alu_valid)&&(alu_illegal))
|
||((alu_valid)&&(alu_illegal))
|
`endif
|
`endif
|
// If we write to the CC register
|
// If we write to the CC register
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
// Or if, in debug mode, we write to the CC register
|
|
||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
|
|
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
|
|
);
|
);
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
// Then if we write the CC register
|
// Then if we write the CC register
|
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
|
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
&&(~wr_reg_id[4])&&(wr_write_cc))
|
// Or if, in debug mode, we write the CC register
|
|
||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
|
|
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
|
|
);
|
);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
gie <= 1'b0;
|
gie <= 1'b0;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
| Line 1226... |
Line 1249... |
if (i_rst)
|
if (i_rst)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
trap <= 1'b1;
|
trap <= 1'b1;
|
else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
|
// else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
|
&&(~i_dbg_data[`CPU_GIE_BIT]))
|
// &&(~i_dbg_data[`CPU_GIE_BIT]))
|
trap <= i_dbg_data[`CPU_TRAP_BIT];
|
// trap <= i_dbg_data[`CPU_TRAP_BIT];
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
trap <= 1'b0;
|
trap <= 1'b0;
|
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
initial ill_err = 1'b0;
|
initial ill_err_i = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ill_err <= 1'b0;
|
ill_err_i <= 1'b0;
|
|
// The debug interface can clear this bit
|
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
|
&&(~wr_reg_vl[`CPU_ILL_BIT]))
|
|
ill_err_i <= 1'b0;
|
|
else if ((alu_valid)&&(alu_illegal)&&(~alu_gie))
|
|
ill_err_i <= 1'b1;
|
|
initial ill_err_u = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
ill_err_u <= 1'b0;
|
|
// The bit is automatically cleared on release from interrupt
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
ill_err <= 1'b0;
|
ill_err_u <= 1'b0;
|
|
// If the supervisor writes to this register, clearing the
|
|
// bit, then clear it
|
|
else if (((~alu_gie)||(dbgv))
|
|
&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
|
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
|
ill_err_u <= 1'b0;
|
else if ((alu_valid)&&(alu_illegal)&&(gie))
|
else if ((alu_valid)&&(alu_illegal)&&(gie))
|
ill_err <= 1'b1;
|
ill_err_u <= 1'b1;
|
`else
|
`else
|
assign ill_err = 1'b0;
|
assign ill_err_u = 1'b0;
|
|
assign ill_err_i = 1'b0;
|
`endif
|
`endif
|
initial bus_err_flag = 1'b0;
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
|
// ever set.
|
|
initial ibus_err_flag = 1'b0;
|
|
always @(posedge i_clk)
|
|
if (i_rst)
|
|
ibus_err_flag <= 1'b0;
|
|
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
|
|
&&(~wr_reg_vl[`CPU_BUSERR_BIT]))
|
|
ibus_err_flag <= 1'b0;
|
|
else if ((bus_err)&&(~alu_gie))
|
|
ibus_err_flag <= 1'b1;
|
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
|
// supervisor mode.
|
|
initial ubus_err_flag = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
bus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
bus_err_flag <= 1'b0;
|
ubus_err_flag <= 1'b0;
|
|
// else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
|
|
// &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
|
|
// &&(~i_dbg_data[`CPU_BUSERR_BIT]))
|
|
// ubus_err_flag <= 1'b0;
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
|
&&(~wr_reg_vl[`CPU_BUSERR_BIT])
|
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
|
ubus_err_flag <= 1'b0;
|
else if ((bus_err)&&(alu_gie))
|
else if ((bus_err)&&(alu_gie))
|
bus_err_flag <= 1'b1;
|
ubus_err_flag <= 1'b1;
|
|
|
//
|
//
|
// Write backs to the PC register, and general increments of it
|
// Write backs to the PC register, and general increments of it
|
// We support two: upc and ipc. If the instruction is normal,
|
// We support two: upc and ipc. If the instruction is normal,
|
// we increment upc, if interrupt level we increment ipc. If
|
// we increment upc, if interrupt level we increment ipc. If
|
| Line 1268... |
Line 1330... |
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
upc <= wr_reg_vl[(AW-1):0];
|
upc <= wr_reg_vl[(AW-1):0];
|
else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
upc <= alu_pc;
|
upc <= alu_pc;
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
|
|
upc <= i_dbg_data[(AW-1):0];
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
ipc <= RESET_ADDRESS;
|
ipc <= RESET_ADDRESS;
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
ipc <= wr_reg_vl[(AW-1):0];
|
ipc <= wr_reg_vl[(AW-1):0];
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
ipc <= alu_pc;
|
ipc <= alu_pc;
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
|
|
ipc <= i_dbg_data[(AW-1):0];
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
pf_pc <= RESET_ADDRESS;
|
pf_pc <= RESET_ADDRESS;
|
else if (w_switch_to_interrupt)
|
else if (w_switch_to_interrupt)
|
pf_pc <= ipc;
|
pf_pc <= ipc;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
pf_pc <= upc;
|
pf_pc <= upc;
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
pf_pc <= wr_reg_vl[(AW-1):0];
|
pf_pc <= wr_reg_vl[(AW-1):0];
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
|
|
pf_pc <= i_dbg_data[(AW-1):0];
|
|
else if (dcd_ce)
|
else if (dcd_ce)
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
|
|
initial new_pc = 1'b1;
|
initial new_pc = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 1308... |
Line 1361... |
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if (w_release_from_interrupt)
|
else if (w_release_from_interrupt)
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
new_pc <= 1'b1;
|
new_pc <= 1'b1;
|
else if ((i_halt)&&(i_dbg_we)
|
|
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
|
|
new_pc <= 1'b1;
|
|
else
|
else
|
new_pc <= 1'b0;
|
new_pc <= 1'b0;
|
|
|
//
|
//
|
// The debug interface
|
// The debug interface
|
| Line 1363... |
Line 1413... |
//
|
//
|
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
|
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
|
|
|
`ifdef DEBUG_SCOPE
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_debug <= {
|
o_debug <= {
|
pf_pc[7:0],
|
pf_pc[7:0],
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
op_ce, alu_ce, mem_ce,
|
op_ce, alu_ce, mem_ce,
|
opA[23:20], opA[3:0],
|
//
|
wr_reg_vl[7:0]
|
master_ce, opvalid_alu, opvalid_mem,
|
|
//
|
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
|
mem_we,
|
|
// ((opvalid_alu)&&(alu_stall))
|
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
|
// opA[23:20], opA[3:0],
|
|
gie, sleep,
|
|
wr_reg_vl[5:0]
|
};
|
};
|
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
