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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Diff between revs 83 and 91
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| Rev 83 |
Rev 91 |
| Line 738... |
Line 738... |
wire w_opvalid;
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wire w_opvalid;
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assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
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assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
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initial opvalid = 1'b0;
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initial opvalid = 1'b0;
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initial opvalid_alu = 1'b0;
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initial opvalid_alu = 1'b0;
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initial opvalid_mem = 1'b0;
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initial opvalid_mem = 1'b0;
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initial opvalid_div = 1'b0;
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initial opvalid_fpu = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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opvalid <= 1'b0;
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opvalid <= 1'b0;
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opvalid_alu <= 1'b0;
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opvalid_alu <= 1'b0;
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| Line 967... |
Line 969... |
||((opF_wr)&&(dcdB_cc))
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||((opF_wr)&&(dcdB_cc))
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// Stall on any ongoing memory operation that
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// Stall on any ongoing memory operation that
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// will write to opB -- captured above
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// will write to opB -- captured above
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// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
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// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
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);
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);
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`else
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// No stalls without pipelining, 'cause how can you have a pipeline
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// hazard without the pipeline?
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assign dcdB_stall = 1'b0;
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`endif
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assign dcdF_stall = ((~dcdF[3])
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assign dcdF_stall = ((~dcdF[3])
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||((dcdA_rd)&&(dcdA_cc))
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||((dcdA_rd)&&(dcdA_cc))
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||((dcdB_rd)&&(dcdB_cc)))
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||((dcdB_rd)&&(dcdB_cc)))
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&&(opvalid)&&(opR_cc);
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&&(opvalid)&&(opR_cc);
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// &&(dcdvalid) is checked for elsewhere
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// &&(dcdvalid) is checked for elsewhere
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`else
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// No stalls without pipelining, 'cause how can you have a pipeline
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// hazard without the pipeline?
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assign dcdB_stall = 1'b0;
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assign dcdF_stall = 1'b0;
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`endif
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//
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//
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//
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//
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// PIPELINE STAGE #4 :: Apply Instruction
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// PIPELINE STAGE #4 :: Apply Instruction
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//
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//
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//
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//
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