| Line 46... |
Line 46... |
// To get access to more than 15 interrupts, chain these together, so
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// To get access to more than 15 interrupts, chain these together, so
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// that one interrupt controller device feeds another.
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// that one interrupt controller device feeds another.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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| Line 69... |
Line 69... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
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module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
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i_brd_ints, o_interrupt_strobe);
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i_brd_ints, o_interrupt);
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parameter IUSED = 15;
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parameter IUSED = 15;
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input i_clk, i_reset;
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input i_clk, i_reset;
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input i_wr;
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input i_wr;
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input [31:0] i_proc_bus;
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input [31:0] i_proc_bus;
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output wire [31:0] o_proc_bus;
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output wire [31:0] o_proc_bus;
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input [(IUSED-1):0] i_brd_ints;
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input [(IUSED-1):0] i_brd_ints;
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output reg o_interrupt_strobe;
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output wire o_interrupt;
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reg [(IUSED-1):0] r_int_state;
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reg [(IUSED-1):0] r_int_state;
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reg [(IUSED-1):0] r_int_enable;
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reg [(IUSED-1):0] r_int_enable;
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wire [(IUSED-1):0] nxt_int_state;
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wire [(IUSED-1):0] nxt_int_state;
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reg r_any, r_interrupt, r_gie;
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reg r_any, r_interrupt, r_gie;
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r_any, { {(15-IUSED){1'b0}}, r_int_state } };
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r_any, { {(15-IUSED){1'b0}}, r_int_state } };
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end else begin
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end else begin
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assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
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assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
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end endgenerate
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end endgenerate
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reg int_condition;
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/*
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initial int_condition = 1'b0;
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reg int_condition;
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initial o_interrupt_strobe = 1'b0;
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initial int_condition = 1'b0;
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always @(posedge i_clk)
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initial o_interrupt_strobe = 1'b0;
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if (i_reset)
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always @(posedge i_clk)
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begin
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if (i_reset)
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int_condition <= 1'b0;
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begin
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o_interrupt_strobe <= 1'b0;
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int_condition <= 1'b0;
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end else if (~r_interrupt) // This might end up generating
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o_interrupt_strobe <= 1'b0;
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begin // many, many, (wild many) interrupts
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end else if (~r_interrupt) // This might end up generating
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int_condition <= 1'b0;
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begin // many, many, (wild many) interrupts
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o_interrupt_strobe <= 1'b0;
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int_condition <= 1'b0;
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end else if ((~int_condition)&&(r_interrupt))
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o_interrupt_strobe <= 1'b0;
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begin
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end else if ((~int_condition)&&(r_interrupt))
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int_condition <= 1'b1;
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begin
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o_interrupt_strobe <= 1'b1;
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int_condition <= 1'b1;
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end else
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o_interrupt_strobe <= 1'b1;
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o_interrupt_strobe <= 1'b0;
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end else
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o_interrupt_strobe <= 1'b0;
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*/
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assign o_interrupt = r_interrupt;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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