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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017-2019, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus,
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`default_nettype none
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//
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module icontrol(i_clk, i_reset, i_wr, i_data, o_data,
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i_brd_ints, o_interrupt);
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i_brd_ints, o_interrupt);
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parameter IUSED = 15;
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parameter IUSED = 15, BW=32;
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input i_clk, i_reset;
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input wire i_clk, i_reset;
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input i_wr;
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input wire i_wr;
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input [31:0] i_proc_bus;
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input wire [BW-1:0] i_data;
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output wire [31:0] o_proc_bus;
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output reg [BW-1:0] o_data;
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input [(IUSED-1):0] i_brd_ints;
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input wire [(IUSED-1):0] i_brd_ints;
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output wire o_interrupt;
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output wire o_interrupt;
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reg [(IUSED-1):0] r_int_state;
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reg [(IUSED-1):0] r_int_state;
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reg [(IUSED-1):0] r_int_enable;
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reg [(IUSED-1):0] r_int_enable;
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wire [(IUSED-1):0] nxt_int_state;
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wire [(IUSED-1):0] nxt_int_state;
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reg r_any, r_interrupt, r_gie;
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reg r_interrupt, r_gie;
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wire w_any;
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assign nxt_int_state = (r_int_state|i_brd_ints);
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assign nxt_int_state = (r_int_state|i_brd_ints);
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initial r_int_state = 0;
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initial r_int_state = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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r_int_state <= 0;
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r_int_state <= 0;
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else if (i_wr)
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else if (i_wr)
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r_int_state <= nxt_int_state & (~i_proc_bus[(IUSED-1):0]);
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r_int_state <= i_brd_ints | (r_int_state & (~i_data[(IUSED-1):0]));
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else
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else
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r_int_state <= nxt_int_state;
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r_int_state <= nxt_int_state;
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initial r_int_enable = 0;
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initial r_int_enable = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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r_int_enable <= 0;
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r_int_enable <= 0;
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else if ((i_wr)&&(i_proc_bus[31]))
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else if ((i_wr)&&(i_data[BW-1]))
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r_int_enable <= r_int_enable | i_proc_bus[(16+IUSED-1):16];
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r_int_enable <= r_int_enable | i_data[(16+IUSED-1):16];
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else if ((i_wr)&&(~i_proc_bus[31]))
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else if ((i_wr)&&(!i_data[BW-1]))
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r_int_enable <= r_int_enable & (~ i_proc_bus[(16+IUSED-1):16]);
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r_int_enable <= r_int_enable & (~ i_data[(16+IUSED-1):16]);
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initial r_gie = 1'b0;
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initial r_gie = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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r_gie <= 1'b0;
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r_gie <= 1'b0;
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else if (i_wr)
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else if (i_wr)
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r_gie <= i_proc_bus[31];
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r_gie <= i_data[BW-1];
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assign w_any = ((r_int_state & r_int_enable) != 0);
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initial r_any = 1'b0;
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always @(posedge i_clk)
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r_any <= ((r_int_state & r_int_enable) != 0);
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initial r_interrupt = 1'b0;
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initial r_interrupt = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_interrupt <= r_gie & r_any;
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if (i_reset)
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r_interrupt <= 1'b0;
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else
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r_interrupt <= (r_gie)&&(w_any);
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generate
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generate
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if (IUSED < 15)
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if (IUSED < 15)
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begin
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begin
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assign o_proc_bus = {
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always @(posedge i_clk)
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o_data <= {
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r_gie, { {(15-IUSED){1'b0}}, r_int_enable },
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r_gie, { {(15-IUSED){1'b0}}, r_int_enable },
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r_any, { {(15-IUSED){1'b0}}, r_int_state } };
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w_any, { {(15-IUSED){1'b0}}, r_int_state } };
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end else begin
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end else begin
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assign o_proc_bus = { r_gie, r_int_enable, r_any, r_int_state };
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always @(posedge i_clk)
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o_data <= { r_gie, r_int_enable, w_any, r_int_state };
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end endgenerate
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end endgenerate
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/*
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reg int_condition;
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initial int_condition = 1'b0;
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initial o_interrupt_strobe = 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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begin
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int_condition <= 1'b0;
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o_interrupt_strobe <= 1'b0;
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end else if (~r_interrupt) // This might end up generating
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begin // many, many, (wild many) interrupts
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int_condition <= 1'b0;
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o_interrupt_strobe <= 1'b0;
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end else if ((~int_condition)&&(r_interrupt))
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begin
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int_condition <= 1'b1;
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o_interrupt_strobe <= 1'b1;
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end else
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o_interrupt_strobe <= 1'b0;
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*/
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assign o_interrupt = r_interrupt;
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assign o_interrupt = r_interrupt;
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// Make verilator happy
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// verilator lint_off UNUSED
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wire [30:0] unused;
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assign unused = i_data[30:0];
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// verilator lint_on UNUSED
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`ifdef FORMAL
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`ifdef ICONTROL
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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initial `ASSUME(i_reset);
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always @(*)
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if (!f_past_valid)
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`ASSUME(i_reset);
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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assert(w_any == 0);
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assert(r_interrupt == 0);
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assert(r_gie == 0);
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assert(r_int_enable == 0);
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end
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset)))
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assert((r_int_state & $past(i_brd_ints))==$past(i_brd_ints));
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always @(posedge i_clk)
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if (((f_past_valid)&&(!$past(i_reset)))
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&&($past(r_int_state) & $past(r_int_enable))
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&&($past(r_gie)) )
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assert(o_interrupt);
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(w_any))&&(!$past(i_wr))&&(!$past(i_reset)))
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assert(w_any);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(r_gie)))
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assert(!o_interrupt);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(w_any)))
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assert(!o_interrupt);
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
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begin
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// Interrupts cannot be cleared, unless they are set
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assert(r_int_state == (($past(i_brd_ints))
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|(($past(r_int_state))&(~$past(i_data[IUSED-1:0])))));
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assert(r_gie == $past(i_data[BW-1]));
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end else if ((f_past_valid)&&(!$past(i_reset)))
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begin
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assert(r_int_state == ($past(r_int_state)|$past(i_brd_ints)));
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assert(r_gie == $past(r_gie));
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end
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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