| Line 187... |
Line 187... |
cfg_len_nonzero <= (|cfg_len);
|
cfg_len_nonzero <= (|cfg_len);
|
|
|
// When the slave wishbone writes, and we are in this
|
// When the slave wishbone writes, and we are in this
|
// (ready) configuration, then allow the DMA to be controlled
|
// (ready) configuration, then allow the DMA to be controlled
|
// and thus to start.
|
// and thus to start.
|
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
|
if ((i_swb_stb)&&(i_swb_we))
|
begin
|
begin
|
case(i_swb_addr)
|
case(i_swb_addr)
|
2'b00: begin
|
2'b00: begin
|
if ((i_swb_data[27:16] == 12'hfed)
|
if ((i_swb_data[27:16] == 12'hfed)
|
&&(cfg_len_nonzero))
|
&&(cfg_len_nonzero))
|
| Line 338... |
Line 338... |
|
|
initial cfg_err = 1'b0;
|
initial cfg_err = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (dma_state == `DMA_IDLE)
|
if (dma_state == `DMA_IDLE)
|
begin
|
begin
|
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
|
if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00))
|
&&(i_swb_addr==2'b00))
|
|
cfg_err <= 1'b0;
|
cfg_err <= 1'b0;
|
end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
|
end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
|
cfg_err <= 1'b1;
|
cfg_err <= 1'b1;
|
|
|
initial last_read_request = 1'b0;
|
initial last_read_request = 1'b0;
|
| Line 364... |
Line 363... |
|
|
initial last_read_ack = 1'b0;
|
initial last_read_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
|
if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
|
begin
|
begin
|
if (i_mwb_ack)
|
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
|
last_read_ack <= (nread+2 == nracks);
|
last_read_ack <= (nread+2 == nracks);
|
else
|
else
|
last_read_ack <= (nread+1 == nracks);
|
last_read_ack <= (nread+1 == nracks);
|
end else
|
end else
|
last_read_ack <= 1'b0;
|
last_read_ack <= 1'b0;
|
| Line 388... |
Line 387... |
|
|
initial last_write_ack = 1'b0;
|
initial last_write_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
|
if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
|
begin
|
begin
|
if (i_mwb_ack)
|
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
|
last_write_ack <= (nwacks+2 == nwritten);
|
last_write_ack <= (nwacks+2 == nwritten);
|
else
|
else
|
last_write_ack <= (nwacks+1 == nwritten);
|
last_write_ack <= (nwacks+1 == nwritten);
|
end else
|
end else
|
last_write_ack <= 1'b0;
|
last_write_ack <= 1'b0;
|
| Line 455... |
Line 454... |
|
|
// Ack any access. We'll quietly ignore any access where we are busy,
|
// Ack any access. We'll quietly ignore any access where we are busy,
|
// but ack it anyway. In other words, before writing to the device,
|
// but ack it anyway. In other words, before writing to the device,
|
// double check that it isn't busy, and then write.
|
// double check that it isn't busy, and then write.
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_swb_ack <= (i_swb_cyc)&&(i_swb_stb);
|
o_swb_ack <= (i_swb_stb);
|
|
|
assign o_swb_stall = 1'b0;
|
assign o_swb_stall = 1'b0;
|
|
|
initial abort = 1'b0;
|
initial abort = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
abort <= (i_rst)||((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
|
abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
|
&&(i_swb_addr == 2'b00)
|
&&(i_swb_addr == 2'b00)
|
&&(i_swb_data == 32'hffed0000));
|
&&(i_swb_data == 32'hffed0000));
|
|
|
endmodule
|
endmodule
|
|
|
