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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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module zipjiffies(i_clk, i_ce,
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module zipjiffies(i_clk, i_ce,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_int);
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o_int);
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parameter BW = 32, VW = (BW-2);
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parameter BW = 32;
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input i_clk, i_ce;
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input i_clk, i_ce;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(BW-1):0] i_wb_data;
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input [(BW-1):0] i_wb_data;
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// Wishbone outputs
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// Wishbone outputs
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assign till_when = int_when-r_counter;
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assign till_when = int_when-r_counter;
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assign till_wb = new_when-r_counter;
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assign till_wb = new_when-r_counter;
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initial new_set = 1'b0;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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// Delay things by a clock to simplify our logic
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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begin
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new_set <= 1'b1;
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// Delay things by a clock to simplify our logic
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new_set <= ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
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// new_when is a don't care when new_set = 0, so don't worry
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// about setting it at all times.
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new_when<= i_wb_data;
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new_when<= i_wb_data;
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end else
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end
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new_set <= 1'b0;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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initial int_set = 1'b0;
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initial int_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_int <= 1'b0;
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o_int <= 1'b0;
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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begin // Interrupts are self-clearing
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// Interrupts are self-clearing
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o_int <= 1'b1; // Set the interrupt flag
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o_int <= 1'b1; // Set the interrupt flag for one clock
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int_set <= 1'b0;// Clear the interrupt
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else if ((new_set)&&(till_wb <= 0))
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end
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o_int <= 1'b1;
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if ((new_set)&&(till_wb > 0))
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int_set <= 1'b1;
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else if ((i_ce)&&(r_counter == int_when))
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int_set <= 1'b0;
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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begin
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int_when <= new_when;
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int_when <= new_when;
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int_set <= ((int_set)||(till_wb>0));
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end
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end
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end
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//
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//
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// Acknowledge any wishbone accesses -- everything we did took only
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// Acknowledge any wishbone accesses -- everything we did took only
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// one clock anyway.
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// one clock anyway.
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