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Line 99... |
reg int_set, new_set;
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reg int_set, new_set;
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reg [(BW-1):0] int_when, new_when;
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reg [(BW-1):0] int_when, new_when;
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wire signed [(BW-1):0] till_when, till_wb;
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wire signed [(BW-1):0] till_when, till_wb;
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assign till_when = int_when-r_counter;
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assign till_when = int_when-r_counter;
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assign till_wb = new_when-r_counter;
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assign till_wb = new_when-r_counter;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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// Delay things by a clock to simplify our logic
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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new_set <= 1'b1;
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new_when<= i_wb_data;
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end else
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new_set <= 1'b0;
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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initial int_set = 1'b0;
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initial int_set = 1'b0;
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initial new_set = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_int <= 1'b0;
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o_int <= 1'b0;
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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if ((i_ce)&&(int_set)&&(r_counter == int_when))
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begin // Interrupts are self-clearing
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begin // Interrupts are self-clearing
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o_int <= 1'b1; // Set the interrupt flag
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o_int <= 1'b1; // Set the interrupt flag
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int_set <= 1'b0;// Clear the interrupt
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int_set <= 1'b0;// Clear the interrupt
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end
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end
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new_set <= 1'b0;
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
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begin
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begin
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int_when <= new_when;
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int_when <= new_when;
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int_set <= ((int_set)||(till_wb>0));
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int_set <= ((int_set)||(till_wb>0));
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end
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end
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// Delay things by a clock to simplify our logic
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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begin
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new_set <= 1'b1;
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new_when<= i_wb_data;
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end
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end
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end
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//
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//
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// Acknowledge any wishbone accesses -- everything we did took only
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// Acknowledge any wishbone accesses -- everything we did took only
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// one clock anyway.
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// one clock anyway.
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//
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//
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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assign o_wb_data = r_counter;
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assign o_wb_data = r_counter;
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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