| Line 65... |
Line 65... |
//
|
//
|
module ziptimer(i_clk, i_rst, i_ce,
|
module ziptimer(i_clk, i_rst, i_ce,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_int);
|
o_int);
|
parameter BW = 32, VW = (BW-1);
|
parameter BW = 32, VW = (BW-1), RELOADABLE=1;
|
input i_clk, i_rst, i_ce;
|
input i_clk, i_rst, i_ce;
|
// Wishbone inputs
|
// Wishbone inputs
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input [(BW-1):0] i_wb_data;
|
input [(BW-1):0] i_wb_data;
|
// Wishbone outputs
|
// Wishbone outputs
|
| Line 77... |
Line 77... |
output wire o_wb_stall;
|
output wire o_wb_stall;
|
output wire [(BW-1):0] o_wb_data;
|
output wire [(BW-1):0] o_wb_data;
|
// Interrupt line
|
// Interrupt line
|
output reg o_int;
|
output reg o_int;
|
|
|
reg r_auto_reload, r_running;
|
reg r_running;
|
reg [(VW-1):0] r_reload_value;
|
|
|
|
wire wb_write;
|
wire wb_write;
|
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
|
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
|
|
|
|
wire auto_reload;
|
|
wire [(VW-1):0] reload_value;
|
|
|
initial r_running = 1'b0;
|
initial r_running = 1'b0;
|
initial r_auto_reload = 1'b0;
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
r_running <= 1'b0;
|
r_running <= 1'b0;
|
else if (wb_write)
|
else if (wb_write)
|
r_running <= (|i_wb_data[(VW-1):0]);
|
r_running <= (|i_wb_data[(VW-1):0]);
|
else if ((o_int)&&(~r_auto_reload))
|
else if ((o_int)&&(~auto_reload))
|
r_running <= 1'b0;
|
r_running <= 1'b0;
|
|
|
|
generate
|
|
if (RELOADABLE != 0)
|
|
begin
|
|
reg r_auto_reload;
|
|
reg [(VW-1):0] r_reload_value;
|
|
|
|
initial r_auto_reload = 1'b0;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_write)
|
if (wb_write)
|
r_auto_reload <= (i_wb_data[(BW-1)]);
|
r_auto_reload <= (i_wb_data[(BW-1)]);
|
|
|
|
assign auto_reload = r_auto_reload;
|
|
|
// If setting auto-reload mode, and the value to other
|
// If setting auto-reload mode, and the value to other
|
// than zero, set the auto-reload value
|
// than zero, set the auto-reload value
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
|
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
|
r_reload_value <= i_wb_data[(VW-1):0];
|
r_reload_value <= i_wb_data[(VW-1):0];
|
|
assign reload_value = r_reload_value;
|
|
end else begin
|
|
assign auto_reload = 1'b0;
|
|
assign reload_value = 0;
|
|
end endgenerate
|
|
|
|
|
reg [(VW-1):0] r_value;
|
reg [(VW-1):0] r_value;
|
initial r_value = 0;
|
initial r_value = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_write)
|
if (wb_write)
|
r_value <= i_wb_data[(VW-1):0];
|
r_value <= i_wb_data[(VW-1):0];
|
else if ((r_running)&&(i_ce)&&(~o_int))
|
else if ((r_running)&&(i_ce)&&(~o_int))
|
r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
|
r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
|
else if ((r_running)&&(r_auto_reload)&&(o_int))
|
else if ((r_running)&&(auto_reload)&&(o_int))
|
r_value <= r_reload_value;
|
r_value <= reload_value;
|
|
|
// Set the interrupt on our last tick.
|
// Set the interrupt on our last tick, as we transition from one to
|
|
// zero.
|
initial o_int = 1'b0;
|
initial o_int = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_ce)
|
if (i_rst)
|
|
o_int <= 1'b0;
|
|
else if (i_ce)
|
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
|
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
|
else
|
else
|
o_int <= 1'b0;
|
o_int <= 1'b0;
|
|
|
initial o_wb_ack = 1'b0;
|
initial o_wb_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
|
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
|
|
assign o_wb_data = { r_auto_reload, r_value };
|
generate
|
|
if (VW < BW-1)
|
|
assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value };
|
|
else
|
|
assign o_wb_data = { auto_reload, r_value };
|
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
