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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 105 and 183
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Rev 105 |
Rev 183 |
Line 47... |
Line 47... |
`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_zip_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=6, START_HALTED=0,
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LGICACHE=8, START_HALTED=0,
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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