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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipbones.v
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// Filename: zipbones.v
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// need to be implemented off-module.
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// need to be implemented off-module.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, 2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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`include "cpudefs.v"
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`include "cpudefs.v"
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//
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//
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module zipbones(i_clk, i_rst,
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module zipbones(i_clk, i_rst,
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// Wishbone master interface from the CPU
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// Wishbone master interface from the CPU
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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// Incoming interrupts
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// Incoming interrupts
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i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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o_dbg_ack, o_dbg_stall, o_dbg_data
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o_dbg_ack, o_dbg_stall, o_dbg_data
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_zip_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
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LGICACHE=8, START_HALTED=0,
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LGICACHE=8, START_HALTED=0;
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AW=ADDRESS_WIDTH;
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localparam AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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output wire [3:0] o_wb_sel;
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input i_wb_ack, i_wb_stall;
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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input i_wb_err;
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input i_wb_err;
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// Incoming interrupts
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// Incoming interrupts
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input i_ext_int;
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input i_ext_int;
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cpu_op_stall, cpu_pf_stall, cpu_i_count;
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cpu_op_stall, cpu_pf_stall, cpu_i_count;
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wire [31:0] cpu_data;
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wire [31:0] cpu_data;
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wire [31:0] cpu_dbg_data;
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wire [31:0] cpu_dbg_data;
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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&&(i_dbg_we)&&(i_dbg_addr));
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&&(i_dbg_we)&&(i_dbg_addr));
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zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
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zipcpu #(.RESET_ADDRESS(RESET_ADDRESS),
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.LGICACHE(LGICACHE),
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.WITH_LOCAL_BUS(0))
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thecpu(i_clk, cpu_reset, i_ext_int,
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thecpu(i_clk, cpu_reset, i_ext_int,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
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i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
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cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
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(i_wb_err)||(cpu_lcl_cyc),
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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cpu_op_stall, cpu_pf_stall, cpu_i_count
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`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_zip_debug
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`endif
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`endif
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);
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);
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