| Line 39... |
Line 39... |
i_ext_int,
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i_ext_int,
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// Our one outgoing interrupt
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// Our one outgoing interrupt
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o_ext_int,
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o_ext_int,
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// Wishbone slave interface for debugging purposes
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// Wishbone slave interface for debugging purposes
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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o_dbg_ack, o_dbg_stall, o_dbg_data);
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o_dbg_ack, o_dbg_stall, o_dbg_data,
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o_zip_debug);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=6, START_HALTED=1,
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LGICACHE=6, START_HALTED=1,
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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| Line 61... |
Line 62... |
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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input [31:0] i_dbg_data;
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input [31:0] i_dbg_data;
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output reg o_dbg_ack;
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output reg o_dbg_ack;
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output wire o_dbg_stall;
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output wire o_dbg_stall;
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output wire [31:0] o_dbg_data;
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output wire [31:0] o_dbg_data;
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//
|
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output wire [31:0] o_zip_debug;
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|
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//
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//
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//
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//
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//
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//
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wire sys_cyc, sys_stb, sys_we;
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wire sys_cyc, sys_stb, sys_we;
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| Line 87... |
Line 90... |
// register.
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// register.
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//
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//
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wire cpu_break, dbg_cmd_write;
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wire cpu_break, dbg_cmd_write;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg [4:0] cmd_addr;
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reg [4:0] cmd_addr;
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wire [1:0] cpu_dbg_cc;
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wire [3:0] cpu_dbg_cc;
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assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
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assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
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//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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| Line 124... |
Line 127... |
wire cpu_reset;
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wire cpu_reset;
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assign cpu_reset = (cmd_reset)||(i_rst);
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assign cpu_reset = (cmd_reset)||(i_rst);
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|
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wire cpu_halt, cpu_dbg_stall;
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wire cpu_halt, cpu_dbg_stall;
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assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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wire [31:0] pic_data;
|
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wire [31:0] cmd_data;
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wire [31:0] cmd_data;
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// Values:
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// Values:
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// 0x0003f -> cmd_addr mask
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// 0x0003f -> cmd_addr mask
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// 0x00040 -> reset
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// 0x00040 -> reset
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// 0x00080 -> PIC interrrupts enabled
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// 0x00080 -> PIC interrrupts enabled
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| Line 138... |
Line 140... |
// 0x00800 -> cmd_clear_pf_cache
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// 0x00800 -> cmd_clear_pf_cache
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// 0x01000 -> cc.sleep
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// 0x01000 -> cc.sleep
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// 0x02000 -> cc.gie
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// 0x02000 -> cc.gie
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// 0x10000 -> External interrupt line is high
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// 0x10000 -> External interrupt line is high
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assign cmd_data = { 7'h00, 8'h00, i_ext_int,
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assign cmd_data = { 7'h00, 8'h00, i_ext_int,
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2'b00, cpu_dbg_cc,
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cpu_dbg_cc,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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pic_data[15], cpu_reset, 1'b0, cmd_addr };
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1'b0, cpu_reset, 1'b0, cmd_addr };
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wire cpu_gie;
|
|
assign cpu_gie = cpu_dbg_cc[1];
|
|
|
|
//
|
//
|
// The CPU itself
|
// The CPU itself
|
//
|
//
|
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
|
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
|
cpu_we, cpu_dbg_we,
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cpu_we, cpu_dbg_we,
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cpu_op_stall, cpu_pf_stall, cpu_i_count;
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cpu_op_stall, cpu_pf_stall, cpu_i_count;
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wire [31:0] cpu_data, wb_data;
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wire [31:0] cpu_data;
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wire cpu_ack, cpu_stall, cpu_err;
|
|
wire [31:0] cpu_dbg_data;
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wire [31:0] cpu_dbg_data;
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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&&(i_dbg_we)&&(i_dbg_addr));
|
&&(i_dbg_we)&&(i_dbg_addr));
|
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
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zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
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thecpu(i_clk, cpu_reset, i_ext_int,
|
thecpu(i_clk, cpu_reset, i_ext_int,
|
| Line 163... |
Line 162... |
i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
|
i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
|
cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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o_wb_cyc, o_wb_stb,
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o_wb_cyc, o_wb_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
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cpu_lcl_cyc, cpu_lcl_stb,
|
o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data,
|
i_wb_err,
|
i_wb_err,
|
cpu_op_stall, cpu_pf_stall, cpu_i_count);
|
cpu_op_stall, cpu_pf_stall, cpu_i_count,
|
|
o_zip_debug);
|
|
|
// Return debug response values
|
// Return debug response values
|
assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
|
assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
|
initial o_dbg_ack = 1'b0;
|
initial o_dbg_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
|
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
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assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
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assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
|
|
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
assign o_ext_int = (cmd_halt) && (~i_wb_stall);
|
|
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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