| Line 7... |
Line 7... |
// Purpose: In the spirit of keeping the Zip CPU small, this implements a
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// Purpose: In the spirit of keeping the Zip CPU small, this implements a
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// Zip System with no peripherals: Any peripherals you wish will
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// Zip System with no peripherals: Any peripherals you wish will
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// need to be implemented off-module.
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// need to be implemented off-module.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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| Line 45... |
Line 45... |
`ifdef DEBUG_SCOPE
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`ifdef DEBUG_SCOPE
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, o_zip_debug
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, o_zip_debug
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`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=6, START_HALTED=1,
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LGICACHE=6, START_HALTED=0,
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AW=ADDRESS_WIDTH;
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AW=ADDRESS_WIDTH;
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input i_clk, i_rst;
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input i_clk, i_rst;
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// Wishbone master
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// Wishbone master
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire o_wb_cyc, o_wb_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [(AW-1):0] o_wb_addr;
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| Line 102... |
Line 102... |
//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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//
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//
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initial cmd_halt = 1'b1;
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initial cmd_halt = START_HALTED;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
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cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
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