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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Diff between revs 69 and 91
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| Rev 69 |
Rev 91 |
| Line 98... |
Line 98... |
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg [4:0] cmd_addr;
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reg [4:0] cmd_addr;
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wire [3:0] cpu_dbg_cc;
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wire [3:0] cpu_dbg_cc;
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assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
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assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
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//
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//
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// Always start us off with an initial reset
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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//
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//
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initial cmd_halt = START_HALTED;
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initial cmd_halt = START_HALTED;
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| Line 111... |
Line 113... |
else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
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cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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initial cmd_clear_pf_cache = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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cmd_clear_pf_cache <= 1'b0;
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cmd_clear_pf_cache <= 1'b0;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_clear_pf_cache <= i_dbg_data[11];
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cmd_clear_pf_cache <= i_dbg_data[11];
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| Line 123... |
Line 126... |
//
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//
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initial cmd_step = 1'b0;
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initial cmd_step = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
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cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
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//
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//
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initial cmd_addr = 5'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (dbg_cmd_write)
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if (dbg_cmd_write)
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cmd_addr <= i_dbg_data[4:0];
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cmd_addr <= i_dbg_data[4:0];
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wire cpu_reset;
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wire cpu_reset;
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