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Line 62... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 171... |
Line 171... |
`endif
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`endif
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);
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);
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parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
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parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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`ifdef OPT_MULTIPLY
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`ifdef OPT_MULTIPLY
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IMPLEMENT_MPY = 1,
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IMPLEMENT_MPY = `OPT_MULTIPLY,
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`else
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`else
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IMPLEMENT_MPY = 0,
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IMPLEMENT_MPY = 0,
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`endif
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`endif
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`ifdef OPT_DIVIDE
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`ifdef OPT_DIVIDE
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IMPLEMENT_DIVIDE=1,
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IMPLEMENT_DIVIDE=1,
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//
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//
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// The WATCHDOG Timer
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// The WATCHDOG Timer
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//
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//
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wire wdt_ack, wdt_stall, wdt_reset;
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wire wdt_ack, wdt_stall, wdt_reset;
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wire [31:0] wdt_data;
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wire [31:0] wdt_data;
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ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
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ziptimer #(32,31,0)
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watchdog(i_clk, cpu_reset, ~cmd_halt,
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sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
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sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
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sys_data,
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sys_data,
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wdt_ack, wdt_stall, wdt_data, wdt_reset);
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wdt_ack, wdt_stall, wdt_data, wdt_reset);
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//
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//
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| Line 521... |
Line 522... |
wire [31:0] dc_data;
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wire [31:0] dc_data;
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wire [(AW-1):0] dc_addr;
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wire [(AW-1):0] dc_addr;
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wire cpu_gbl_cyc;
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wire cpu_gbl_cyc;
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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`ifdef INCLUDE_DMA_CONTROLLER
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`ifdef INCLUDE_DMA_CONTROLLER
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wbdmac #(AW) dma_controller(i_clk,
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wbdmac #(AW) dma_controller(i_clk, cpu_reset,
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sys_cyc, dmac_stb, sys_we,
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sys_cyc, dmac_stb, sys_we,
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sys_addr[1:0], sys_data,
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sys_addr[1:0], sys_data,
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dmac_ack, dmac_stall, dmac_data,
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dmac_ack, dmac_stall, dmac_data,
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// Need the outgoing DMAC wishbone bus
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// Need the outgoing DMAC wishbone bus
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dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
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dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
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| Line 533... |
Line 534... |
// External device interrupts
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// External device interrupts
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{ 1'b0, alt_int_vector, 1'b0,
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{ 1'b0, alt_int_vector, 1'b0,
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main_int_vector[14:1], 1'b0 },
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main_int_vector[14:1], 1'b0 },
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// DMAC interrupt, for upon completion
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// DMAC interrupt, for upon completion
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dmac_int);
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dmac_int);
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// Whether or not the CPU wants the bus, and
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// thus we must kick the DMAC off.
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// However, the logic required for this
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// override never worked well, so here
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// we just don't use it.
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// cpu_gbl_cyc);
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`else
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`else
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reg r_dmac_ack;
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reg r_dmac_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_dmac_ack <= (sys_cyc)&&(dmac_stb);
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r_dmac_ack <= (sys_cyc)&&(dmac_stb);
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assign dmac_ack = r_dmac_ack;
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assign dmac_ack = r_dmac_ack;
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Line 670... |
wire [31:0] cpu_data, wb_data;
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wire [31:0] cpu_data, wb_data;
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wire cpu_ack, cpu_stall, cpu_err;
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wire cpu_ack, cpu_stall, cpu_err;
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wire [31:0] cpu_dbg_data;
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wire [31:0] cpu_dbg_data;
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assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
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assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
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&&(dbg_we)&&(dbg_addr));
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&&(dbg_we)&&(dbg_addr));
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zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE, IMPLEMENT_MPY,
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zipcpu #(
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IMPLEMENT_DIVIDE, IMPLEMENT_FPU, IMPLEMENT_LOCK)
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.RESET_ADDRESS(RESET_ADDRESS),
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.ADDRESS_WIDTH(ADDRESS_WIDTH),
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.LGICACHE(LGICACHE),
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.IMPLEMENT_MPY(IMPLEMENT_MPY),
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.IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE),
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.IMPLEMENT_FPU(IMPLEMENT_FPU),
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.IMPLEMENT_LOCK(IMPLEMENT_LOCK)
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)
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thecpu(i_clk, cpu_reset, pic_interrupt,
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thecpu(i_clk, cpu_reset, pic_interrupt,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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dbg_idata, cpu_dbg_stall, cpu_dbg_data,
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cpu_dbg_cc, cpu_break,
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cpu_dbg_cc, cpu_break,
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cpu_gbl_cyc, cpu_gbl_stb,
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cpu_gbl_cyc, cpu_gbl_stb,
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Line 726... |
// Return debug response values
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// Return debug response values
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assign dbg_odata = (~dbg_addr)?cmd_data
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assign dbg_odata = (~dbg_addr)?cmd_data
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:((~cmd_addr[5])?cpu_dbg_data : wb_data);
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:((~cmd_addr[5])?cpu_dbg_data : wb_data);
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initial dbg_ack = 1'b0;
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initial dbg_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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dbg_ack <= (dbg_cyc)&&(~dbg_stall);
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dbg_ack <= (dbg_cyc)&&(dbg_stb)&&(~dbg_stall);
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assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
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assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
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// Now for the external wishbone bus
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// Now for the external wishbone bus
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// Need to arbitrate between the flash cache and the CPU
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// Need to arbitrate between the flash cache and the CPU
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// The way this works, though, the CPU will stall once the flash
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// The way this works, though, the CPU will stall once the flash
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