| Line 306... |
Line 306... |
//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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//
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//
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initial cmd_halt = 1'b1;
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initial cmd_halt = START_HALTED;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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else if (dbg_cmd_write)
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else if (dbg_cmd_write)
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
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else if ((cmd_step)||(cpu_break))
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else if ((cmd_step)||(cpu_break))
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cmd_halt <= 1'b1;
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cmd_halt <= 1'b1;
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|
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initial cmd_clear_pf_cache = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
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&&((dbg_idata[11])||(dbg_idata[6]));
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&&((dbg_idata[11])||(dbg_idata[6]));
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//
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//
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initial cmd_step = 1'b0;
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initial cmd_step = 1'b0;
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| Line 554... |
Line 555... |
`endif
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`endif
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|
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wire ctri_sel, ctri_stall;
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wire ctri_sel, ctri_stall;
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reg ctri_ack;
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reg ctri_ack;
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wire [31:0] ctri_data;
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wire [31:0] ctri_data;
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assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
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assign ctri_sel = (sys_stb)&&(sys_addr == `CTRINT);
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always @(posedge i_clk)
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always @(posedge i_clk)
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ctri_ack <= ctri_sel;
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ctri_ack <= ctri_sel;
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assign ctri_stall = 1'b0;
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assign ctri_stall = 1'b0;
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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`ifdef INCLUDE_ACCOUNTING_COUNTERS
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//
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//
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| Line 658... |
Line 659... |
|
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wire pic_stall;
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wire pic_stall;
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assign pic_stall = 1'b0;
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assign pic_stall = 1'b0;
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reg pic_ack;
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reg pic_ack;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
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pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL);
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|
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//
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//
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// The CPU itself
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// The CPU itself
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//
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//
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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