| Line 168... |
Line 168... |
o_dbg_ack, o_dbg_stall, o_dbg_data
|
o_dbg_ack, o_dbg_stall, o_dbg_data
|
`ifdef DEBUG_SCOPE
|
`ifdef DEBUG_SCOPE
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, o_cpu_debug
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, o_cpu_debug
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`endif
|
`endif
|
);
|
);
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parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
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`ifdef OPT_MULTIPLY
|
`ifdef OPT_MULTIPLY
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IMPLEMENT_MPY = `OPT_MULTIPLY,
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IMPLEMENT_MPY = `OPT_MULTIPLY,
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`else
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`else
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IMPLEMENT_MPY = 0,
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IMPLEMENT_MPY = 0,
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| Line 521... |
Line 521... |
wire dmac_ack, dmac_stall;
|
wire dmac_ack, dmac_stall;
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
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wire [31:0] dc_data;
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wire [31:0] dc_data;
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wire [(AW-1):0] dc_addr;
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wire [(AW-1):0] dc_addr;
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wire cpu_gbl_cyc;
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wire cpu_gbl_cyc;
|
|
wire [31:0] dmac_int_vec;
|
|
assign dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
|
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main_int_vector[14:1], 1'b0 };
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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assign dmac_stb = (sys_stb)&&(sys_addr[4]);
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`ifdef INCLUDE_DMA_CONTROLLER
|
`ifdef INCLUDE_DMA_CONTROLLER
|
wbdmac #(AW) dma_controller(i_clk, cpu_reset,
|
wbdmac #(AW) dma_controller(i_clk, cpu_reset,
|
sys_cyc, dmac_stb, sys_we,
|
sys_cyc, dmac_stb, sys_we,
|
sys_addr[1:0], sys_data,
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sys_addr[1:0], sys_data,
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dmac_ack, dmac_stall, dmac_data,
|
dmac_ack, dmac_stall, dmac_data,
|
// Need the outgoing DMAC wishbone bus
|
// Need the outgoing DMAC wishbone bus
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_ack, dc_stall, ext_idata, dc_err,
|
dc_ack, dc_stall, ext_idata, dc_err,
|
// External device interrupts
|
// External device interrupts
|
{ 1'b0, alt_int_vector, 1'b0,
|
dmac_int_vec,
|
main_int_vector[14:1], 1'b0 },
|
|
// DMAC interrupt, for upon completion
|
// DMAC interrupt, for upon completion
|
dmac_int);
|
dmac_int);
|
`else
|
`else
|
reg r_dmac_ack;
|
reg r_dmac_ack;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
| Line 780... |
Line 782... |
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:((wdbus_ack)?wdbus_data:(ext_idata))));
|
:((wdbus_ack)?wdbus_data:(ext_idata))));
|
|
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
| wdt_stall | ctri_stall | actr_stall
|
| wdt_stall | ctri_stall | actr_stall
|
| pic_stall | dmac_stall);
|
| pic_stall | dmac_stall); // Always 1'b0!
|
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
|
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
|
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
|
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
|
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
|
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
|
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
|
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
|
|
|
