| Line 100... |
Line 100... |
`define JIFFIES 4'h7 // Sets IVEC[1]
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`define JIFFIES 4'h7 // Sets IVEC[1]
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`define MSTR_TASK_CTR 4'h8
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`define MSTR_TASK_CTR 4'h8
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`define MSTR_MSTL_CTR 4'h9
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`define MSTR_MSTL_CTR 4'h9
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`define MSTR_PSTL_CTR 4'ha
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`define MSTR_PSTL_CTR 4'ha
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`define MSTR_ASTL_CTR 4'hb
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`define MSTR_INST_CTR 4'hb
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`define USER_TASK_CTR 4'hc
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`define USER_TASK_CTR 4'hc
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`define USER_MSTL_CTR 4'hd
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`define USER_MSTL_CTR 4'hd
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`define USER_PSTL_CTR 4'he
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`define USER_PSTL_CTR 4'he
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`define USER_ASTL_CTR 4'hf
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`define USER_INST_CTR 4'hf
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`define CACHEBASE 16'hc010 //
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`define CACHEBASE 16'hc010 //
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// `define RTC_CLOCK 32'hc0000008 // A global something
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// `define RTC_CLOCK 32'hc0000008 // A global something
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// `define BITREV 32'hc0000003
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// `define BITREV 32'hc0000003
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//
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//
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| Line 199... |
Line 199... |
// register.
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// register.
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//
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//
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wire cpu_break, dbg_cmd_write;
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wire cpu_break, dbg_cmd_write;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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reg [5:0] cmd_addr;
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reg [5:0] cmd_addr;
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wire [3:0] cpu_dbg_cc;
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wire [1:0] cpu_dbg_cc;
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assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
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assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
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//
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//
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initial cmd_reset = 1'b1;
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initial cmd_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
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| Line 248... |
Line 248... |
// 0x00200 -> cmd_stall
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// 0x00200 -> cmd_stall
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// 0x00400 -> cmd_halt
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// 0x00400 -> cmd_halt
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// 0x00800 -> cmd_clear_pf_cache
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// 0x00800 -> cmd_clear_pf_cache
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// 0x01000 -> cc.sleep
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// 0x01000 -> cc.sleep
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// 0x02000 -> cc.gie
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// 0x02000 -> cc.gie
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// 0x04000 -> cc.step
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// 0x08000 -> cc.break_en
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// 0x10000 -> External interrupt line is high
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// 0x10000 -> External interrupt line is high
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assign cmd_data = { 15'h00, i_ext_int, cpu_dbg_cc,
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assign cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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pic_data[15], cpu_reset, cmd_addr };
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pic_data[15], cpu_reset, cmd_addr };
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`ifdef USE_TRAP
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`ifdef USE_TRAP
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//
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//
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Line 334... |
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// Master Instruction counter
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// Master Instruction counter
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wire mic_ack, mic_stall, mic_int;
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wire mic_ack, mic_stall, mic_int;
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wire [31:0] mic_data;
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wire [31:0] mic_data;
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zipcounter mins_ctr(i_clk,(cpu_i_count), sys_cyc,
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zipcounter mins_ctr(i_clk,(cpu_i_count), sys_cyc,
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(sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
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(sys_stb)&&(sys_addr == `MSTR_INST_CTR),
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sys_we, sys_data,
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sys_we, sys_data,
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mic_ack, mic_stall, mic_data, mic_int);
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mic_ack, mic_stall, mic_data, mic_int);
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//
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//
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// The user counters are different from those of the master. They will
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// The user counters are different from those of the master. They will
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| Line 372... |
Line 370... |
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// User instruction counter
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// User instruction counter
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wire uic_ack, uic_stall, uic_int;
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wire uic_ack, uic_stall, uic_int;
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wire [31:0] uic_data;
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wire [31:0] uic_data;
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zipcounter uins_ctr(i_clk,(cpu_i_count), sys_cyc,
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zipcounter uins_ctr(i_clk,(cpu_i_count), sys_cyc,
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(sys_stb)&&(sys_addr == `USER_ASTL_CTR),
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(sys_stb)&&(sys_addr == `USER_INST_CTR),
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sys_we, sys_data,
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sys_we, sys_data,
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uic_ack, uic_stall, uic_data, uic_int);
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uic_ack, uic_stall, uic_data, uic_int);
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// A little bit of pre-cleanup (actr = accounting counters)
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// A little bit of pre-cleanup (actr = accounting counters)
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wire actr_ack, actr_stall;
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wire actr_ack, actr_stall;
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| Line 502... |
Line 500... |
initial dbg_ack = 1'b0;
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initial dbg_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
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dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
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((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
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((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
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assign dbg_stall=(dbg_addr)&&(dbg_cyc)
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assign dbg_stall=(dbg_addr)&&(dbg_cyc)
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&&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
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&&((cpu_cyc)||((cmd_halt)&&(~cpu_halt))
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||(cpu_dbg_stall));
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// Now for the external wishbone bus
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// Now for the external wishbone bus
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// Need to arbitrate between the flash cache and the CPU
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// Need to arbitrate between the flash cache and the CPU
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// The way this works, though, the CPU will stall once the flash
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// The way this works, though, the CPU will stall once the flash
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// cache gets access to the bus--the CPU will be stuck until the
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// cache gets access to the bus--the CPU will be stuck until the
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