| Line 94... |
Line 94... |
// earlier, or into the memops.v file. This also required my wishbone bus
|
// earlier, or into the memops.v file. This also required my wishbone bus
|
// arbiter to maintain the bus selection as well, so that got updated ...
|
// arbiter to maintain the bus selection as well, so that got updated ...
|
// you get the picture. But, the bottom line is that I no longer need this
|
// you get the picture. But, the bottom line is that I no longer need this
|
// delay.
|
// delay.
|
//
|
//
|
// `define DELAY_EXT_BUS // Required no longer!k
|
// `define DELAY_EXT_BUS // Required no longer!
|
//
|
//
|
//
|
//
|
// If space is tight, you might not wish to have your performance and
|
// If space is tight, you might not wish to have your performance and
|
// accounting counters, so let's make those optional here
|
// accounting counters, so let's make those optional here
|
// Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
|
// Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
|
| Line 111... |
Line 111... |
//
|
//
|
// Now, where am I placing all of my peripherals?
|
// Now, where am I placing all of my peripherals?
|
`define PERIPHBASE 32'hc0000000
|
`define PERIPHBASE 32'hc0000000
|
`define INTCTRL 5'h0 //
|
`define INTCTRL 5'h0 //
|
`define WATCHDOG 5'h1 // Interrupt generates reset signal
|
`define WATCHDOG 5'h1 // Interrupt generates reset signal
|
// `define CACHECTRL 5'h2 // Sets IVEC[0]
|
`define BUSWATCHDOG 5'h2 // Sets IVEC[0]
|
`define CTRINT 5'h3 // Sets IVEC[5]
|
`define CTRINT 5'h3 // Sets IVEC[5]
|
`define TIMER_A 5'h4 // Sets IVEC[4]
|
`define TIMER_A 5'h4 // Sets IVEC[4]
|
`define TIMER_B 5'h5 // Sets IVEC[3]
|
`define TIMER_B 5'h5 // Sets IVEC[3]
|
`define TIMER_C 5'h6 // Sets IVEC[2]
|
`define TIMER_C 5'h6 // Sets IVEC[2]
|
`define JIFFIES 5'h7 // Sets IVEC[1]
|
`define JIFFIES 5'h7 // Sets IVEC[1]
|
| Line 159... |
Line 159... |
i_ext_int,
|
i_ext_int,
|
// Our one outgoing interrupt
|
// Our one outgoing interrupt
|
o_ext_int,
|
o_ext_int,
|
// Wishbone slave interface for debugging purposes
|
// Wishbone slave interface for debugging purposes
|
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
|
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
|
o_dbg_ack, o_dbg_stall, o_dbg_data);
|
o_dbg_ack, o_dbg_stall, o_dbg_data,
|
|
o_cpu_debug);
|
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
|
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
|
LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
|
LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
|
// Derived parameters
|
// Derived parameters
|
AW=ADDRESS_WIDTH;
|
AW=ADDRESS_WIDTH;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
| Line 182... |
Line 183... |
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
|
input i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
|
input [31:0] i_dbg_data;
|
input [31:0] i_dbg_data;
|
output wire o_dbg_ack;
|
output wire o_dbg_ack;
|
output wire o_dbg_stall;
|
output wire o_dbg_stall;
|
output wire [31:0] o_dbg_data;
|
output wire [31:0] o_dbg_data;
|
|
//
|
|
output wire [31:0] o_cpu_debug;
|
|
|
wire [31:0] ext_idata;
|
wire [31:0] ext_idata;
|
|
|
// Delay the debug port by one clock, to meet timing requirements
|
// Delay the debug port by one clock, to meet timing requirements
|
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
|
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
|
| Line 233... |
Line 236... |
// register.
|
// register.
|
//
|
//
|
wire cpu_break, dbg_cmd_write;
|
wire cpu_break, dbg_cmd_write;
|
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
|
reg cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
|
reg [5:0] cmd_addr;
|
reg [5:0] cmd_addr;
|
wire [1:0] cpu_dbg_cc;
|
wire [3:0] cpu_dbg_cc;
|
assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
|
assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
|
//
|
//
|
initial cmd_reset = 1'b1;
|
initial cmd_reset = 1'b1;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
|
cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
|
| Line 250... |
Line 253... |
cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
|
cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
|
else if ((cmd_step)||(cpu_break))
|
else if ((cmd_step)||(cpu_break))
|
cmd_halt <= 1'b1;
|
cmd_halt <= 1'b1;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_rst)
|
cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
|
cmd_clear_pf_cache <= 1'b0;
|
&&((dbg_idata[11])||(dbg_idata[6]));
|
else if (dbg_cmd_write)
|
|
cmd_clear_pf_cache <= dbg_idata[11];
|
|
else
|
|
cmd_clear_pf_cache <= 1'b0;
|
|
//
|
//
|
initial cmd_step = 1'b0;
|
initial cmd_step = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
|
cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
|
//
|
//
|
| Line 284... |
Line 283... |
// 0x00800 -> cmd_clear_pf_cache
|
// 0x00800 -> cmd_clear_pf_cache
|
// 0x01000 -> cc.sleep
|
// 0x01000 -> cc.sleep
|
// 0x02000 -> cc.gie
|
// 0x02000 -> cc.gie
|
// 0x10000 -> External interrupt line is high
|
// 0x10000 -> External interrupt line is high
|
assign cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
|
assign cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
|
2'b00, cpu_dbg_cc,
|
cpu_dbg_cc,
|
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
|
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
|
pic_data[15], cpu_reset, cmd_addr };
|
pic_data[15], cpu_reset, cmd_addr };
|
wire cpu_gie;
|
wire cpu_gie;
|
assign cpu_gie = cpu_dbg_cc[1];
|
assign cpu_gie = cpu_dbg_cc[1];
|
|
|
| Line 313... |
Line 312... |
sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
|
sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
|
sys_data,
|
sys_data,
|
wdt_ack, wdt_stall, wdt_data, wdt_reset);
|
wdt_ack, wdt_stall, wdt_data, wdt_reset);
|
|
|
//
|
//
|
// Position two ... unclaimed / unused
|
// Position two, a second watchdog timer--this time for the wishbone
|
//
|
// bus, in order to tell/find wishbone bus lockups. In its current
|
wire cache_stall;
|
// configuration, it cannot be configured and all bus accesses must
|
assign cache_stall = 1'b0;
|
// take less than the number written to this register.
|
reg cache_ack;
|
//
|
|
reg wdbus_ack;
|
|
reg [(AW-1):0] r_wdbus_data;
|
|
wire [31:0] wdbus_data;
|
|
wire [14:0] wdbus_ignored_data;
|
|
wire reset_wdbus_timer, wdbus_int, wdbus_ack_ignored, wdbus_stall;
|
|
assign reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack)));
|
|
// o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
|
// i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
|
|
ziptimer #(15) watchbus(i_clk, (cpu_reset), o_wb_cyc,
|
|
reset_wdbus_timer, reset_wdbus_timer, 1'b1, 15'h2000,
|
|
wdbus_ack_ignored, wdbus_stall, wdbus_ignored_data,
|
|
wdbus_int);
|
|
initial r_wdbus_data = 0;
|
|
always @(posedge i_clk)
|
|
if (wdbus_int)
|
|
r_wdbus_data = o_wb_addr;
|
|
assign wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data };
|
|
initial wdbus_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
cache_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02);
|
wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02));
|
|
|
// Counters -- for performance measurement and accounting
|
// Counters -- for performance measurement and accounting
|
//
|
//
|
// Here's the stuff we'll be counting ....
|
// Here's the stuff we'll be counting ....
|
//
|
//
|
wire cpu_op_stall, cpu_pf_stall, cpu_i_count;
|
wire cpu_op_stall, cpu_pf_stall, cpu_i_count;
|
| Line 447... |
Line 465... |
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
|
wire [31:0] dc_data;
|
wire [31:0] dc_data;
|
wire [(AW-1):0] dc_addr;
|
wire [(AW-1):0] dc_addr;
|
wire cpu_gbl_cyc;
|
wire cpu_gbl_cyc;
|
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
|
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
|
|
// `define INCLUDE_DMA_CONTROLLER
|
|
`ifdef INCLUDE_DMA_CONTROLLER
|
wbdmac #(AW) dma_controller(i_clk,
|
wbdmac #(AW) dma_controller(i_clk,
|
sys_cyc, dmac_stb, sys_we,
|
sys_cyc, dmac_stb, sys_we,
|
sys_addr[1:0], sys_data,
|
sys_addr[1:0], sys_data,
|
dmac_ack, dmac_stall, dmac_data,
|
dmac_ack, dmac_stall, dmac_data,
|
// Need the outgoing DMAC wishbone bus
|
// Need the outgoing DMAC wishbone bus
|
| Line 460... |
Line 480... |
{ {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
|
{ {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
|
// DMAC interrupt, for upon completion
|
// DMAC interrupt, for upon completion
|
dmac_int,
|
dmac_int,
|
// Whether or not the CPU wants the bus
|
// Whether or not the CPU wants the bus
|
cpu_gbl_cyc);
|
cpu_gbl_cyc);
|
|
`else
|
|
reg r_dmac_ack;
|
|
always @(posedge i_clk)
|
|
r_dmac_ack <= (sys_cyc)&&(dmac_stb);
|
|
assign dmac_ack = r_dmac_ack;
|
|
assign dmac_data = 32'h000;
|
|
assign dmac_stall = 1'b0;
|
|
|
|
assign dc_cyc = 1'b0;
|
|
assign dc_stb = 1'b0;
|
|
assign dc_we = 1'b0;
|
|
assign dc_addr = { (AW) {1'b0} };
|
|
assign dc_data = 32'h00;
|
|
|
|
assign dmac_int = 1'b0;
|
|
`endif
|
|
|
|
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
//
|
//
|
// Counter Interrupt controller
|
// Counter Interrupt controller
|
| Line 569... |
Line 605... |
cpu_gbl_cyc, cpu_gbl_stb,
|
cpu_gbl_cyc, cpu_gbl_stb,
|
cpu_lcl_cyc, cpu_lcl_stb,
|
cpu_lcl_cyc, cpu_lcl_stb,
|
cpu_we, cpu_addr, cpu_data,
|
cpu_we, cpu_addr, cpu_data,
|
cpu_ack, cpu_stall, wb_data,
|
cpu_ack, cpu_stall, wb_data,
|
cpu_err,
|
cpu_err,
|
cpu_op_stall, cpu_pf_stall, cpu_i_count);
|
cpu_op_stall, cpu_pf_stall, cpu_i_count,
|
|
o_cpu_debug);
|
|
|
// Now, arbitrate the bus ... first for the local peripherals
|
// Now, arbitrate the bus ... first for the local peripherals
|
// For the debugger to have access to the local system bus, the
|
// For the debugger to have access to the local system bus, the
|
// following must be true:
|
// following must be true:
|
// (dbg_cyc) The debugger must request the bus
|
// (dbg_cyc) The debugger must request the bus
|
| Line 616... |
Line 653... |
wire ext_cyc, ext_stb, ext_we, ext_err;
|
wire ext_cyc, ext_stb, ext_we, ext_err;
|
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
|
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
|
cpu_ext_err;
|
cpu_ext_err;
|
wire [(AW-1):0] ext_addr;
|
wire [(AW-1):0] ext_addr;
|
wire [31:0] ext_odata;
|
wire [31:0] ext_odata;
|
wbpriarbiter #(32,AW) dmacvcpu(i_clk, i_rst,
|
wbpriarbiter #(32,AW) dmacvcpu(i_clk,
|
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
|
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
|
cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
|
cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
|
dc_ack, dc_stall, dc_err,
|
dc_ack, dc_stall, dc_err,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
| Line 629... |
Line 666... |
`ifdef DELAY_EXT_BUS
|
`ifdef DELAY_EXT_BUS
|
busdelay #(AW,32) extbus(i_clk,
|
busdelay #(AW,32) extbus(i_clk,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
|
ext_ack, ext_stall, ext_idata, ext_err,
|
ext_ack, ext_stall, ext_idata, ext_err,
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
|
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
|
i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
|
`else
|
`else
|
assign o_wb_cyc = ext_cyc;
|
assign o_wb_cyc = ext_cyc;
|
assign o_wb_stb = ext_stb;
|
assign o_wb_stb = ext_stb;
|
assign o_wb_we = ext_we;
|
assign o_wb_we = ext_we;
|
assign o_wb_addr = ext_addr;
|
assign o_wb_addr = ext_addr;
|
assign o_wb_data = ext_odata;
|
assign o_wb_data = ext_odata;
|
assign ext_ack = i_wb_ack;
|
assign ext_ack = i_wb_ack;
|
assign ext_stall = i_wb_stall;
|
assign ext_stall = i_wb_stall;
|
assign ext_idata = i_wb_data;
|
assign ext_idata = i_wb_data;
|
assign ext_err = i_wb_err;
|
assign ext_err = (i_wb_err)||(wdbus_int);
|
`endif
|
`endif
|
|
|
wire tmr_ack;
|
wire tmr_ack;
|
assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
|
assign tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
|
wire [31:0] tmr_data;
|
wire [31:0] tmr_data;
|
| Line 652... |
Line 689... |
:(tmc_ack ? tmc_data
|
:(tmc_ack ? tmc_data
|
:jif_data));
|
:jif_data));
|
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
|
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
|
:((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
|
:((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
|
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
|
:(ext_idata)));
|
:((wdbus_ack)?wdbus_data:(ext_idata))));
|
|
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
|
| wdt_stall | ctri_stall | actr_stall
|
| wdt_stall | ctri_stall | actr_stall
|
| pic_stall | dmac_stall | cache_stall);
|
| pic_stall | dmac_stall | wdbus_stall);
|
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
|
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
|
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|cache_ack);
|
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
|
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
|
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
|
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
|
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
|
|
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
assign o_ext_int = (cmd_halt) && (~cpu_stall);
|
|
|
