| Line 181... |
Line 181... |
IMPLEMENT_DIVIDE=1,
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IMPLEMENT_DIVIDE=1,
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`else
|
`else
|
IMPLEMENT_DIVIDE=0,
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IMPLEMENT_DIVIDE=0,
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`endif
|
`endif
|
`ifdef OPT_IMPLEMENT_FPU
|
`ifdef OPT_IMPLEMENT_FPU
|
IMPLEMENT_FPU=0,
|
|
`else
|
|
IMPLEMENT_FPU=1,
|
IMPLEMENT_FPU=1,
|
|
`else
|
|
IMPLEMENT_FPU=0,
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`endif
|
`endif
|
IMPLEMENT_LOCK=1,
|
IMPLEMENT_LOCK=1,
|
// Derived parameters
|
// Derived parameters
|
AW=ADDRESS_WIDTH;
|
AW=ADDRESS_WIDTH;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
| Line 508... |
Line 508... |
wire actr_stall;
|
wire actr_stall;
|
wire [31:0] actr_data;
|
wire [31:0] actr_data;
|
assign actr_stall = 1'b0;
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assign actr_stall = 1'b0;
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assign actr_data = 32'h0000;
|
assign actr_data = 32'h0000;
|
|
|
wire utc_int, uoc_int, upc_int, uic_int;
|
|
wire mtc_int, moc_int, mpc_int, mic_int;
|
|
assign mtc_int = 1'b0;
|
assign mtc_int = 1'b0;
|
assign moc_int = 1'b0;
|
assign moc_int = 1'b0;
|
assign mpc_int = 1'b0;
|
assign mpc_int = 1'b0;
|
assign mic_int = 1'b0;
|
assign mic_int = 1'b0;
|
assign utc_int = 1'b0;
|
assign utc_int = 1'b0;
|
| Line 570... |
Line 568... |
assign dc_data = 32'h00;
|
assign dc_data = 32'h00;
|
|
|
assign dmac_int = 1'b0;
|
assign dmac_int = 1'b0;
|
`endif
|
`endif
|
|
|
wire ctri_sel;
|
wire ctri_sel, ctri_stall;
|
reg ctri_ack;
|
reg ctri_ack;
|
|
wire [31:0] ctri_data;
|
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
|
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
ctri_ack <= ctri_sel;
|
ctri_ack <= ctri_sel;
|
|
assign ctri_stall = 1'b0;
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS
|
//
|
//
|
// Counter Interrupt controller
|
// Counter Interrupt controller
|
//
|
//
|
wire ctri_stall;
|
|
wire [31:0] ctri_data;
|
|
|
|
generate
|
generate
|
if (EXTERNAL_INTERRUPTS <= 9)
|
if (EXTERNAL_INTERRUPTS <= 9)
|
begin
|
begin
|
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel),
|
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel),
|
sys_data, ctri_data, alt_int_vector[7:0],
|
sys_data, ctri_data, alt_int_vector[7:0],
|
| Line 596... |
Line 593... |
sys_data, ctri_data,
|
sys_data, ctri_data,
|
alt_int_vector[(EXTERNAL_INTERRUPTS-1):0],
|
alt_int_vector[(EXTERNAL_INTERRUPTS-1):0],
|
ctri_int);
|
ctri_int);
|
end endgenerate
|
end endgenerate
|
|
|
assign ctri_stall = 1'b0;
|
|
`else // INCLUDE_ACCOUNTING_COUNTERS
|
`else // INCLUDE_ACCOUNTING_COUNTERS
|
|
|
generate
|
generate
|
if (EXTERNAL_INTERRUPTS <= 9)
|
if (EXTERNAL_INTERRUPTS <= 9)
|
begin
|
begin
|
wire ctri_stall, ctri_int;
|
|
wire [31:0] ctri_data;
|
|
assign ctri_stall = 1'b0;
|
assign ctri_stall = 1'b0;
|
assign ctri_data = 32'h0000;
|
assign ctri_data = 32'h0000;
|
assign ctri_int = 1'b0;
|
assign ctri_int = 1'b0;
|
end else begin
|
end else begin
|
icontrol #(EXTERNAL_INTERRUPTS-9)
|
icontrol #(EXTERNAL_INTERRUPTS-9)
|
