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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: div_tb.cpp
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// Filename: div_tb.cpp
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <signal.h>
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#include <signal.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <time.h>
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#include <time.h>
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#include <ctype.h>
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#include <ctype.h>
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#include "verilated.h"
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#include "verilated.h"
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#include "Vdiv.h"
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#include "Vdiv.h"
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#ifdef NEW_VERILATOR
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#define VVAR(A) div__DOT_ ## A
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#else
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#define VVAR(A) v__DOT_ ## A
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#endif
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#define r_busy VVAR(_r_busy)
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#define pre_sign VVAR(_pre_sign)
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#define r_sign VVAR(_r_sign)
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#define r_z VVAR(_r_z)
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#define r_bit VVAR(_r_bit)
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#define last_bit VVAR(_last_bit)
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#define r_dividend VVAR(_r_dividend)
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#define r_divisor VVAR(_r_divisor)
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#define vdiff VVAR(_diff)
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#include "testb.h"
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#include "testb.h"
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// #include "twoc.h"
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// #include "twoc.h"
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#define DIVASSERT(A) do { if (!(A)) { closetrace(); } assert(A); } while(0)
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#define DIVASSERT(A) do { if (!(A)) { closetrace(); } assert(A); } while(0)
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} *str = '\0';
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} *str = '\0';
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}
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}
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void dbgdump(void) {
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void dbgdump(void) {
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char outstr[2048], *s;
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char outstr[2048], *s;
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sprintf(outstr, "Tick %4ld %s%s%s%s%s%s%s %2d(%s= 0)",
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sprintf(outstr, "Tick %4lld %s%s%s%s%s%s%s %2d(%s= 0)",
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m_tickcount,
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(unsigned long long)m_tickcount,
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(m_core->o_busy)?"B":" ",
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(m_core->o_busy)?"B":" ",
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(m_core->v__DOT__r_busy)?"R":" ",
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(m_core->r_busy)?"R":" ",
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(m_core->o_valid)?"V":" ",
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(m_core->o_valid)?"V":" ",
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(m_core->i_wr)?"W":" ",
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(m_core->i_wr)?"W":" ",
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(m_core->v__DOT__pre_sign)?"+":" ",
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(m_core->pre_sign)?"+":" ",
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(m_core->v__DOT__r_sign)?"-":" ",
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(m_core->r_sign)?"-":" ",
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(m_core->v__DOT__r_z)?"Z":" ",
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(m_core->r_z)?"Z":" ",
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m_core->v__DOT__r_bit,
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m_core->r_bit,
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(m_core->v__DOT__last_bit)?"=":"!");
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(m_core->last_bit)?"=":"!");
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s = &outstr[strlen(outstr)];
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s = &outstr[strlen(outstr)];
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sprintf(s, "%s\n%10s %40s",s, "Div","");
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sprintf(s, "%s\n%10s %40s",s, "Div","");
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s = &s[strlen(s)];
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s = &s[strlen(s)];
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bprint( s, 32, m_core->v__DOT__r_dividend);
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bprint( s, 32, m_core->r_dividend);
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s=&s[strlen(s)];
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s=&s[strlen(s)];
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sprintf(s, "%s\n%10s ",s, "Div"); s = &s[strlen(s)];
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sprintf(s, "%s\n%10s ",s, "Div"); s = &s[strlen(s)];
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bprint( s, 64, m_core->v__DOT__r_divisor);
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bprint( s, 64, m_core->r_divisor);
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s=&s[strlen(s)];
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s=&s[strlen(s)];
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sprintf(s, "%s\n%10s %40s",s, "Q",""); s=&s[strlen(s)];
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sprintf(s, "%s\n%10s %40s",s, "Q",""); s=&s[strlen(s)];
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bprint( s, 32, m_core->o_quotient); s = &s[strlen(s)];
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bprint( s, 32, m_core->o_quotient); s = &s[strlen(s)];
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sprintf(s, "%s\n%10s %38s",s, "Diff","");
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sprintf(s, "%s\n%10s %38s",s, "Diff","");
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s=&s[strlen(s)];
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s=&s[strlen(s)];
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bprint( s, 33, m_core->v__DOT__diff); s = &s[strlen(s)];
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bprint( s, 33, m_core->vdiff); s = &s[strlen(s)];
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strcat(s, "\n");
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strcat(s, "\n");
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puts(outstr);
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puts(outstr);
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}
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}
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void tick(void) {
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void tick(void) {
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// The test bench is supposed to assert that we are idle when
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// The test bench is supposed to assert that we are idle when
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// we come in here.
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// we come in here.
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DIVASSERT(m_core->o_busy == 0);
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DIVASSERT(m_core->o_busy == 0);
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// Request a divide
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// Request a divide
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m_core->i_rst = 0;
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m_core->i_reset = 0;
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m_core->i_wr = 1;
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m_core->i_wr = 1;
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m_core->i_signed = (issigned)?1:0;
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m_core->i_signed = (issigned)?1:0;
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m_core->i_numerator = n;
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m_core->i_numerator = n;
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m_core->i_denominator = d;
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m_core->i_denominator = d;
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