Line 1... |
Line 1... |
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/archures.c binutils-2.27-zip/bfd/archures.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/archures.c binutils-2.27-zip/bfd/archures.c
|
--- binutils-2.27/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400
|
--- binutils-2.27-original/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400
|
+++ binutils-2.27-zip/bfd/archures.c 2017-01-04 14:22:45.000000000 -0500
|
+++ binutils-2.27-zip/bfd/archures.c 2017-01-04 14:22:45.000000000 -0500
|
@@ -525,6 +525,8 @@
|
@@ -525,6 +525,8 @@
|
.#define bfd_mach_nios2r2 2
|
.#define bfd_mach_nios2r2 2
|
. bfd_arch_visium, {* Visium *}
|
. bfd_arch_visium, {* Visium *}
|
.#define bfd_mach_visium 1
|
.#define bfd_mach_visium 1
|
Line 24... |
Line 24... |
&bfd_z8k_arch,
|
&bfd_z8k_arch,
|
+ &bfd_zip_arch,
|
+ &bfd_zip_arch,
|
#endif
|
#endif
|
0
|
0
|
};
|
};
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/bfd-in2.h binutils-2.27-zip/bfd/bfd-in2.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/bfd-in2.h binutils-2.27-zip/bfd/bfd-in2.h
|
--- binutils-2.27/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
|
--- binutils-2.27-original/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
|
+++ binutils-2.27-zip/bfd/bfd-in2.h 2017-01-04 22:04:11.000000000 -0500
|
+++ binutils-2.27-zip/bfd/bfd-in2.h 2017-01-04 22:04:11.000000000 -0500
|
@@ -2336,6 +2336,8 @@
|
@@ -2336,6 +2336,8 @@
|
#define bfd_mach_nios2r2 2
|
#define bfd_mach_nios2r2 2
|
bfd_arch_visium, /* Visium */
|
bfd_arch_visium, /* Visium */
|
#define bfd_mach_visium 1
|
#define bfd_mach_visium 1
|
Line 59... |
Line 59... |
+ BFD_RELOC_ZIP_LLO,
|
+ BFD_RELOC_ZIP_LLO,
|
+ BFD_RELOC_ZIP_BREV,
|
+ BFD_RELOC_ZIP_BREV,
|
BFD_RELOC_UNUSED };
|
BFD_RELOC_UNUSED };
|
|
|
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
|
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/config.bfd binutils-2.27-zip/bfd/config.bfd
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/config.bfd binutils-2.27-zip/bfd/config.bfd
|
--- binutils-2.27/bfd/config.bfd 2016-08-03 03:36:50.000000000 -0400
|
--- binutils-2.27-original/bfd/config.bfd 2016-08-03 03:36:50.000000000 -0400
|
+++ binutils-2.27-zip/bfd/config.bfd 2016-12-31 17:11:00.961307172 -0500
|
+++ binutils-2.27-zip/bfd/config.bfd 2016-12-31 17:11:00.961307172 -0500
|
@@ -1742,6 +1742,10 @@
|
@@ -1742,6 +1742,10 @@
|
targ_underscore=yes
|
targ_underscore=yes
|
;;
|
;;
|
|
|
Line 73... |
Line 73... |
+ ;;
|
+ ;;
|
+
|
+
|
*-*-ieee*)
|
*-*-ieee*)
|
targ_defvec=ieee_vec
|
targ_defvec=ieee_vec
|
;;
|
;;
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure binutils-2.27-zip/bfd/configure
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/configure binutils-2.27-zip/bfd/configure
|
--- binutils-2.27/bfd/configure 2016-08-03 04:33:36.000000000 -0400
|
--- binutils-2.27-original/bfd/configure 2016-08-03 04:33:36.000000000 -0400
|
+++ binutils-2.27-zip/bfd/configure 2016-12-31 17:12:22.360697343 -0500
|
+++ binutils-2.27-zip/bfd/configure 2016-12-31 17:12:22.360697343 -0500
|
@@ -14542,6 +14542,7 @@
|
@@ -14542,6 +14542,7 @@
|
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
|
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
|
z80_coff_vec) tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
|
z80_coff_vec) tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
|
z8k_coff_vec) tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
|
z8k_coff_vec) tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
|
Line 94... |
Line 94... |
+ COREFILE=netbsd-core.lo
|
+ COREFILE=netbsd-core.lo
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
case "$COREFILE" in
|
case "$COREFILE" in
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure.ac binutils-2.27-zip/bfd/configure.ac
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/configure.ac binutils-2.27-zip/bfd/configure.ac
|
--- binutils-2.27/bfd/configure.ac 2016-08-03 03:36:50.000000000 -0400
|
--- binutils-2.27-original/bfd/configure.ac 2016-08-03 03:36:50.000000000 -0400
|
+++ binutils-2.27-zip/bfd/configure.ac 2016-12-31 17:13:38.600136486 -0500
|
+++ binutils-2.27-zip/bfd/configure.ac 2016-12-31 17:13:38.600136486 -0500
|
@@ -717,6 +717,7 @@
|
@@ -717,6 +717,7 @@
|
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
|
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
|
z80_coff_vec) tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
|
z80_coff_vec) tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
|
z8k_coff_vec) tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
|
z8k_coff_vec) tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
|
Line 115... |
Line 115... |
+ COREFILE=netbsd-core.lo
|
+ COREFILE=netbsd-core.lo
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
case "$COREFILE" in
|
case "$COREFILE" in
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/cpu-zip.c binutils-2.27-zip/bfd/cpu-zip.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/cpu-zip.c binutils-2.27-zip/bfd/cpu-zip.c
|
--- binutils-2.27/bfd/cpu-zip.c 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/bfd/cpu-zip.c 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/bfd/cpu-zip.c 2017-01-04 14:26:27.000000000 -0500
|
+++ binutils-2.27-zip/bfd/cpu-zip.c 2017-01-04 14:26:27.000000000 -0500
|
@@ -0,0 +1,65 @@
|
@@ -0,0 +1,65 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: tc-zip.c
|
+// Filename: tc-zip.c
|
Line 184... |
Line 184... |
+ bfd_arch_default_fill, // Default fill.
|
+ bfd_arch_default_fill, // Default fill.
|
+ NULL // Pointer to next bfd_arch_info_type in
|
+ NULL // Pointer to next bfd_arch_info_type in
|
+ // the same family.
|
+ // the same family.
|
+};
|
+};
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/archures.texi binutils-2.27-zip/bfd/doc/archures.texi
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/archures.texi binutils-2.27-zip/bfd/doc/archures.texi
|
--- binutils-2.27/bfd/doc/archures.texi 2016-08-03 04:36:22.000000000 -0400
|
--- binutils-2.27-original/bfd/doc/archures.texi 2016-08-03 04:36:22.000000000 -0400
|
+++ binutils-2.27-zip/bfd/doc/archures.texi 2016-12-31 17:14:43.103668704 -0500
|
+++ binutils-2.27-zip/bfd/doc/archures.texi 2016-12-31 17:14:43.103668704 -0500
|
@@ -492,6 +492,8 @@
|
@@ -492,6 +492,8 @@
|
#define bfd_mach_nios2r2 2
|
#define bfd_mach_nios2r2 2
|
bfd_arch_visium, /* Visium */
|
bfd_arch_visium, /* Visium */
|
#define bfd_mach_visium 1
|
#define bfd_mach_visium 1
|
+ bfd_mach_zip,
|
+ bfd_mach_zip,
|
+#define bfd_mach_zip 0
|
+#define bfd_mach_zip 0
|
bfd_arch_last
|
bfd_arch_last
|
@};
|
@};
|
@end example
|
@end example
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/bfd.info binutils-2.27-zip/bfd/doc/bfd.info
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/bfd.info binutils-2.27-zip/bfd/doc/bfd.info
|
--- binutils-2.27/bfd/doc/bfd.info 2016-08-03 04:36:22.000000000 -0400
|
--- binutils-2.27-original/bfd/doc/bfd.info 2016-08-03 04:36:22.000000000 -0400
|
+++ binutils-2.27-zip/bfd/doc/bfd.info 2017-01-04 14:40:21.000000000 -0500
|
+++ binutils-2.27-zip/bfd/doc/bfd.info 2017-01-04 14:40:21.000000000 -0500
|
@@ -8466,6 +8466,8 @@
|
@@ -8466,6 +8466,8 @@
|
#define bfd_mach_nios2r2 2
|
#define bfd_mach_nios2r2 2
|
bfd_arch_visium, /* Visium */
|
bfd_arch_visium, /* Visium */
|
#define bfd_mach_visium 1
|
#define bfd_mach_visium 1
|
+ bfd_arch_zip, /* ZipCPU */
|
+ bfd_arch_zip, /* ZipCPU */
|
+ #define bfd_mach_zip 0
|
+ #define bfd_mach_zip 0
|
bfd_arch_last
|
bfd_arch_last
|
};
|
};
|
|
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/reloc.texi binutils-2.27-zip/bfd/doc/reloc.texi
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/reloc.texi binutils-2.27-zip/bfd/doc/reloc.texi
|
--- binutils-2.27/bfd/doc/reloc.texi 2016-08-03 04:36:22.000000000 -0400
|
--- binutils-2.27-original/bfd/doc/reloc.texi 2016-08-03 04:36:22.000000000 -0400
|
+++ binutils-2.27-zip/bfd/doc/reloc.texi 2016-12-31 17:17:15.950640091 -0500
|
+++ binutils-2.27-zip/bfd/doc/reloc.texi 2016-12-31 17:17:15.950640091 -0500
|
@@ -4214,6 +4214,19 @@
|
@@ -4214,6 +4214,19 @@
|
@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL
|
@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL
|
Visium Relocations.
|
Visium Relocations.
|
@end deffn
|
@end deffn
|
Line 231... |
Line 231... |
+ZipCPU relocations
|
+ZipCPU relocations
|
+@end deffn
|
+@end deffn
|
|
|
@example
|
@example
|
|
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/elf32-zip.c binutils-2.27-zip/bfd/elf32-zip.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/elf32-zip.c binutils-2.27-zip/bfd/elf32-zip.c
|
--- binutils-2.27/bfd/elf32-zip.c 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/bfd/elf32-zip.c 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/bfd/elf32-zip.c 2017-01-24 13:54:25.214097101 -0500
|
+++ binutils-2.27-zip/bfd/elf32-zip.c 2017-01-24 13:54:25.214097101 -0500
|
@@ -0,0 +1,1134 @@
|
@@ -0,0 +1,1134 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: tc-zip.c
|
+// Filename: tc-zip.c
|
Line 1369... |
Line 1369... |
+ /* backend_data: */
|
+ /* backend_data: */
|
+ &elf32_bed
|
+ &elf32_bed
|
+};
|
+};
|
+#endif
|
+#endif
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/libbfd.h binutils-2.27-zip/bfd/libbfd.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/libbfd.h binutils-2.27-zip/bfd/libbfd.h
|
--- binutils-2.27/bfd/libbfd.h 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/bfd/libbfd.h 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/bfd/libbfd.h 2017-01-04 22:04:11.000000000 -0500
|
+++ binutils-2.27-zip/bfd/libbfd.h 2017-01-04 22:04:11.000000000 -0500
|
@@ -3125,6 +3125,16 @@
|
@@ -3125,6 +3125,16 @@
|
"BFD_RELOC_VISIUM_HI16_PCREL",
|
"BFD_RELOC_VISIUM_HI16_PCREL",
|
"BFD_RELOC_VISIUM_LO16_PCREL",
|
"BFD_RELOC_VISIUM_LO16_PCREL",
|
"BFD_RELOC_VISIUM_IM16_PCREL",
|
"BFD_RELOC_VISIUM_IM16_PCREL",
|
Line 1389... |
Line 1389... |
+ "BFD_RELOC_ZIP_LLO",
|
+ "BFD_RELOC_ZIP_LLO",
|
+ "BFD_RELOC_ZIP_BREV",
|
+ "BFD_RELOC_ZIP_BREV",
|
"@@overflow: BFD_RELOC_UNUSED@@",
|
"@@overflow: BFD_RELOC_UNUSED@@",
|
};
|
};
|
#endif
|
#endif
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.am binutils-2.27-zip/bfd/Makefile.am
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/Makefile.am binutils-2.27-zip/bfd/Makefile.am
|
--- binutils-2.27/bfd/Makefile.am 2016-08-03 03:36:50.000000000 -0400
|
--- binutils-2.27-original/bfd/Makefile.am 2016-08-03 03:36:50.000000000 -0400
|
+++ binutils-2.27-zip/bfd/Makefile.am 2016-12-31 17:26:07.151146300 -0500
|
+++ binutils-2.27-zip/bfd/Makefile.am 2016-12-31 17:26:07.151146300 -0500
|
@@ -173,7 +173,8 @@
|
@@ -173,7 +173,8 @@
|
cpu-xstormy16.lo \
|
cpu-xstormy16.lo \
|
cpu-xtensa.lo \
|
cpu-xtensa.lo \
|
cpu-z80.lo \
|
cpu-z80.lo \
|
Line 1428... |
Line 1428... |
elf32-xtensa.c \
|
elf32-xtensa.c \
|
+ elf32-zip.c \
|
+ elf32-zip.c \
|
elf32.c \
|
elf32.c \
|
elflink.c \
|
elflink.c \
|
elfxx-sparc.c \
|
elfxx-sparc.c \
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.in binutils-2.27-zip/bfd/Makefile.in
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/Makefile.in binutils-2.27-zip/bfd/Makefile.in
|
--- binutils-2.27/bfd/Makefile.in 2016-08-03 04:06:27.000000000 -0400
|
--- binutils-2.27-original/bfd/Makefile.in 2016-08-03 04:06:27.000000000 -0400
|
+++ binutils-2.27-zip/bfd/Makefile.in 2017-01-04 14:29:55.000000000 -0500
|
+++ binutils-2.27-zip/bfd/Makefile.in 2017-01-04 14:29:55.000000000 -0500
|
@@ -505,7 +505,8 @@
|
@@ -505,7 +505,8 @@
|
cpu-xstormy16.lo \
|
cpu-xstormy16.lo \
|
cpu-xtensa.lo \
|
cpu-xtensa.lo \
|
cpu-z80.lo \
|
cpu-z80.lo \
|
Line 1475... |
Line 1475... |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-z8k.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-z8k.Plo@am__quote@
|
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-zip.Plo@am__quote@
|
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-zip.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/demo64.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/demo64.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf1.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf1.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf2.Plo@am__quote@
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf2.Plo@am__quote@
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/merge.c binutils-2.27-zip/bfd/merge.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/merge.c binutils-2.27-zip/bfd/merge.c
|
--- binutils-2.27/bfd/merge.c 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/bfd/merge.c 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/bfd/merge.c 2017-01-02 14:48:54.000000000 -0500
|
+++ binutils-2.27-zip/bfd/merge.c 2017-01-02 14:48:54.000000000 -0500
|
@@ -826,7 +826,7 @@
|
@@ -826,7 +826,7 @@
|
else
|
else
|
{
|
{
|
contents = NULL;
|
contents = NULL;
|
- pos = sec->output_section->filepos + sec->output_offset;
|
- pos = sec->output_section->filepos + sec->output_offset;
|
+ pos = sec->output_section->filepos + sec->output_offset * bfd_octets_per_byte(output_bfd);
|
+ pos = sec->output_section->filepos + sec->output_offset * bfd_octets_per_byte(output_bfd);
|
if (bfd_seek (output_bfd, pos, SEEK_SET) != 0)
|
if (bfd_seek (output_bfd, pos, SEEK_SET) != 0)
|
return FALSE;
|
return FALSE;
|
}
|
}
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/reloc.c binutils-2.27-zip/bfd/reloc.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/reloc.c binutils-2.27-zip/bfd/reloc.c
|
--- binutils-2.27/bfd/reloc.c 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/bfd/reloc.c 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/bfd/reloc.c 2017-01-04 22:03:52.000000000 -0500
|
+++ binutils-2.27-zip/bfd/reloc.c 2017-01-04 22:03:52.000000000 -0500
|
@@ -7697,7 +7697,32 @@
|
@@ -7697,7 +7697,32 @@
|
BFD_RELOC_VISIUM_IM16_PCREL
|
BFD_RELOC_VISIUM_IM16_PCREL
|
ENUMDOC
|
ENUMDOC
|
Visium Relocations.
|
Visium Relocations.
|
Line 1524... |
Line 1524... |
+ENUMDOC
|
+ENUMDOC
|
+ ZipCPU value relocations
|
+ ZipCPU value relocations
|
ENDSENUM
|
ENDSENUM
|
BFD_RELOC_UNUSED
|
BFD_RELOC_UNUSED
|
CODE_FRAGMENT
|
CODE_FRAGMENT
|
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/targets.c binutils-2.27-zip/bfd/targets.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/targets.c binutils-2.27-zip/bfd/targets.c
|
--- binutils-2.27/bfd/targets.c 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/bfd/targets.c 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/bfd/targets.c 2016-12-31 17:37:14.021847080 -0500
|
+++ binutils-2.27-zip/bfd/targets.c 2016-12-31 17:37:14.021847080 -0500
|
@@ -910,6 +910,7 @@
|
@@ -910,6 +910,7 @@
|
extern const bfd_target xtensa_elf32_le_vec;
|
extern const bfd_target xtensa_elf32_le_vec;
|
extern const bfd_target z80_coff_vec;
|
extern const bfd_target z80_coff_vec;
|
extern const bfd_target z8k_coff_vec;
|
extern const bfd_target z8k_coff_vec;
|
Line 1544... |
Line 1544... |
+
|
+
|
+ &zip_elf32_vec,
|
+ &zip_elf32_vec,
|
#endif /* not SELECT_VECS */
|
#endif /* not SELECT_VECS */
|
|
|
/* Always support S-records, for convenience. */
|
/* Always support S-records, for convenience. */
|
diff -Naur '--exclude=*.swp' binutils-2.27/binutils/readelf.c binutils-2.27-zip/binutils/readelf.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/binutils/readelf.c binutils-2.27-zip/binutils/readelf.c
|
--- binutils-2.27/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/binutils/readelf.c 2016-12-31 17:40:19.908241961 -0500
|
+++ binutils-2.27-zip/binutils/readelf.c 2016-12-31 17:40:19.908241961 -0500
|
@@ -154,6 +154,7 @@
|
@@ -154,6 +154,7 @@
|
#include "elf/xgate.h"
|
#include "elf/xgate.h"
|
#include "elf/xstormy16.h"
|
#include "elf/xstormy16.h"
|
#include "elf/xtensa.h"
|
#include "elf/xtensa.h"
|
Line 1608... |
Line 1608... |
case EM_XC16X:
|
case EM_XC16X:
|
+ case EM_ZIP:
|
+ case EM_ZIP:
|
return reloc_type == 0;
|
return reloc_type == 0;
|
|
|
case EM_AARCH64:
|
case EM_AARCH64:
|
diff -Naur '--exclude=*.swp' binutils-2.27/config.sub binutils-2.27-zip/config.sub
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/config.sub binutils-2.27-zip/config.sub
|
--- binutils-2.27/config.sub 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/config.sub 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/config.sub 2017-01-11 14:20:34.804049801 -0500
|
+++ binutils-2.27-zip/config.sub 2017-01-11 14:20:34.804049801 -0500
|
@@ -316,7 +316,7 @@
|
@@ -316,7 +316,7 @@
|
| visium \
|
| visium \
|
| we32k \
|
| we32k \
|
| x86 | xc16x | xstormy16 | xtensa \
|
| x86 | xc16x | xstormy16 | xtensa \
|
Line 1635... |
Line 1635... |
+ os=-elf
|
+ os=-elf
|
+ ;;
|
+ ;;
|
|
|
# We use `pc' rather than `unknown'
|
# We use `pc' rather than `unknown'
|
# because (1) that's what they normally are, and
|
# because (1) that's what they normally are, and
|
diff -Naur '--exclude=*.swp' binutils-2.27/configure binutils-2.27-zip/configure
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/configure binutils-2.27-zip/configure
|
--- binutils-2.27/configure 2016-08-03 03:54:55.000000000 -0400
|
--- binutils-2.27-original/configure 2016-08-03 03:54:55.000000000 -0400
|
+++ binutils-2.27-zip/configure 2017-01-08 20:37:33.566336786 -0500
|
+++ binutils-2.27-zip/configure 2017-01-08 20:37:33.566336786 -0500
|
@@ -3548,6 +3548,9 @@
|
@@ -3548,6 +3548,9 @@
|
ft32-*-*)
|
ft32-*-*)
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
;;
|
;;
|
Line 1668... |
Line 1668... |
+ noconfigdirs="$noconfigdirs gdb gprof"
|
+ noconfigdirs="$noconfigdirs gdb gprof"
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
diff -Naur '--exclude=*.swp' binutils-2.27/configure.ac binutils-2.27-zip/configure.ac
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/configure.ac binutils-2.27-zip/configure.ac
|
--- binutils-2.27/configure.ac 2016-08-03 04:37:38.000000000 -0400
|
--- binutils-2.27-original/configure.ac 2016-08-03 04:37:38.000000000 -0400
|
+++ binutils-2.27-zip/configure.ac 2017-01-08 20:41:54.836485336 -0500
|
+++ binutils-2.27-zip/configure.ac 2017-01-08 20:41:54.836485336 -0500
|
@@ -884,6 +884,9 @@
|
@@ -884,6 +884,9 @@
|
ft32-*-*)
|
ft32-*-*)
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
;;
|
;;
|
Line 1701... |
Line 1701... |
+ noconfigdirs="$noconfigdirs ${libgcj} gdb sim gprof"
|
+ noconfigdirs="$noconfigdirs ${libgcj} gdb sim gprof"
|
+ ;;
|
+ ;;
|
esac
|
esac
|
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.c binutils-2.27-zip/gas/config/tc-zip.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/config/tc-zip.c binutils-2.27-zip/gas/config/tc-zip.c
|
--- binutils-2.27/gas/config/tc-zip.c 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/config/tc-zip.c 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/config/tc-zip.c 2017-03-15 23:03:15.801504568 -0400
|
+++ binutils-2.27-zip/gas/config/tc-zip.c 2019-02-14 20:54:05.341671631 -0500
|
@@ -0,0 +1,3340 @@
|
@@ -0,0 +1,3403 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: tc-zip.c
|
+// Filename: tc-zip.c
|
+//
|
+//
|
+// Project: Zip CPU backend for GNU Binutils
|
+// Project: Zip CPU backend for GNU Binutils
|
Line 1726... |
Line 1726... |
+// Creator: Dan Gisselquist, Ph.D.
|
+// Creator: Dan Gisselquist, Ph.D.
|
+// Gisselquist Technology, LLC
|
+// Gisselquist Technology, LLC
|
+//
|
+//
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
+// Copyright (C) 2016-2018, Gisselquist Technology, LLC
|
+//
|
+//
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// This program is free software (firmware): you can redistribute it and/or
|
+// modify it under the terms of the GNU General Public License as published
|
+// modify it under the terms of the GNU General Public License as published
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
+// your option) any later version.
|
+// your option) any later version.
|
Line 1875... |
Line 1875... |
+ memcpy((char *)nw, (char *)old, sizeof(ZIPIS));
|
+ memcpy((char *)nw, (char *)old, sizeof(ZIPIS));
|
+
|
+
|
+ return nw;
|
+ return nw;
|
+}
|
+}
|
+
|
+
|
|
+static int fits_within(int nbits, int value) {
|
|
+ // -2 fits_within two bits
|
|
+ // -1 fits_within two bits
|
|
+ // 1 fits_within two bits
|
|
+ // 2 does not
|
|
+ //
|
|
+ if (value > 0)
|
|
+ return (value < (1l<<(nbits-1))) ? 1:0;
|
|
+ else
|
|
+ return (value >= -(1l<<(nbits-1))) ? 1:0;
|
|
+}
|
|
+
|
+static uint32_t
|
+static uint32_t
|
+zip_brev(uint32_t v) {
|
+zip_brev(uint32_t v) {
|
+ unsigned r=0, b;
|
+ unsigned r=0, b;
|
+
|
+
|
+ for(b=0; b<32; b++, v>>=1)
|
+ for(b=0; b<32; b++, v>>=1)
|
Line 1945... |
Line 1957... |
+ pzipm->r[insn->i_areg].m_value = insn->i_imm;
|
+ pzipm->r[insn->i_areg].m_value = insn->i_imm;
|
+ pzipm->r[insn->i_areg].m_addsy = insn->i_rp->r_sym;
|
+ pzipm->r[insn->i_areg].m_addsy = insn->i_rp->r_sym;
|
+ pzipm->r[insn->i_areg].m_subsy = NULL;
|
+ pzipm->r[insn->i_areg].m_subsy = NULL;
|
+ return;
|
+ return;
|
+ }
|
+ }
|
+ } else if (insn->i_rp) {
|
+ } else if (insn->i_rp)
|
+ bknown = MACH_VUNKNOWN;
|
+ bknown = MACH_VUNKNOWN;
|
+ } else if (ZIP_RNONE == insn->i_breg)
|
+ else if (ZIP_RNONE == insn->i_breg)
|
+ // B-Op is an immediate only
|
+ // B-Op is an immediate only
|
+ bknown = MACH_VKNOWN;
|
+ bknown = MACH_VKNOWN;
|
+ else if (insn->i_breg >= ZIP_CC)
|
+ else if (insn->i_breg >= ZIP_CC)
|
+ bknown = MACH_VUNKNOWN;
|
+ bknown = MACH_VUNKNOWN;
|
+ else if (insn->i_imm == 0)
|
+ else if (insn->i_imm == 0)
|
Line 2003... |
Line 2015... |
+ else
|
+ else
|
+ bv = NULL;
|
+ bv = NULL;
|
+
|
+
|
+ if (ZIPC_ALWAYS != insn->i_cnd) {
|
+ if (ZIPC_ALWAYS != insn->i_cnd) {
|
+#ifdef ZIP_DEBUG
|
+#ifdef ZIP_DEBUG
|
+ fprintf(stderr, "MACHINE, CONDITIONAL\n");
|
+ fprintf(stderr, "\tMACHINE, CONDITIONAL operation\n");
|
+#endif
|
+#endif
|
+ if ((ZIPO_LDILO == insn->i_op)
|
+ if ((ZIPO_LDILO == insn->i_op)
|
+ &&((av->m_known == MACH_VKNOWN)
|
+ &&((av->m_known == MACH_VKNOWN)
|
+ ||(av->m_known == MACH_VUPPERKNOWN)))
|
+ ||(av->m_known == MACH_VUPPERKNOWN))) {
|
+ av->m_known = MACH_VUPPERKNOWN;
|
+ av->m_known = MACH_VUPPERKNOWN;
|
+ else if ((ZIPO_LDI == insn->i_op)||(ZIPO_LDIn == insn->i_op))
|
+ } else if ((ZIPO_LDI == insn->i_op)||(ZIPO_LDIn == insn->i_op)){
|
+ ; // We'll catch this in a moment
|
+ if (((av->m_known == MACH_VKNOWN)
|
+ else
|
+ ||(av->m_known == MACH_VUPPERKNOWN))
|
|
+ &&(((insn->i_imm ^ av->m_value)&& ~0x0ffff)==0)) {
|
|
+ av->m_known = MACH_VUPPERKNOWN;
|
|
+ } else
|
|
+ av->m_known = MACH_VUNKNOWN;
|
|
+ } else {
|
+ av->m_known = MACH_VUNKNOWN;
|
+ av->m_known = MACH_VUNKNOWN;
|
|
+}
|
+ } switch(insn->i_op) {
|
+ } switch(insn->i_op) {
|
+ case ZIPO_SUB:
|
+ case ZIPO_SUB:
|
+ av->m_known = (av->m_known==MACH_VKNOWN)
|
+ av->m_known = (av->m_known==MACH_VKNOWN)
|
+ ? MACH_VKNOWN:MACH_VUNKNOWN;
|
+ ? MACH_VKNOWN:MACH_VUNKNOWN;
|
+ av->m_value -= bval;
|
+ av->m_value -= bval;
|
Line 2160... |
Line 2178... |
+
|
+
|
+ pzipm->r[ZIP_CC].m_known = MACH_VUNKNOWN;
|
+ pzipm->r[ZIP_CC].m_known = MACH_VUNKNOWN;
|
+ pzipm->r[ZIP_PC].m_known = MACH_VUNKNOWN;
|
+ pzipm->r[ZIP_PC].m_known = MACH_VUNKNOWN;
|
+}
|
+}
|
+
|
+
|
|
+static int zip_findnearreg_machine(MACHINEREGS *pzipm, unsigned value) {
|
|
+ int bestrg = ZIP_RNONE, bestd, d;
|
|
+ int rg;
|
|
+
|
|
+ bestd = 0x7fffffff;
|
|
+ bestrg= ZIP_RNONE;
|
|
+
|
|
+ for(rg=0; rg<ZIP_CC; rg++) {
|
|
+ if (pzipm->r[rg].m_known == MACH_VUNKNOWN)
|
|
+ continue;
|
|
+ if (pzipm->r[rg].m_known == MACH_VSYMKNOWN)
|
|
+ continue;
|
|
+ if (pzipm->r[rg].m_known == MACH_VUPPERKNOWN)
|
|
+ continue;
|
|
+ gas_assert(pzipm->r[rg].m_known == MACH_VKNOWN);
|
|
+
|
|
+ if (pzipm->r[rg].m_addsy)
|
|
+ continue;
|
|
+ if (pzipm->r[rg].m_subsy)
|
|
+ continue;
|
|
+
|
|
+ d = abs(pzipm->r[rg].m_value - value);
|
|
+ if (d < bestd) {
|
|
+ bestd = d;
|
|
+ bestrg = rg;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (fits_within(18,bestd))
|
|
+ return bestrg;
|
|
+ return ZIP_RNONE;
|
|
+}
|
|
+
|
+#ifdef ZIP_DEBUG
|
+#ifdef ZIP_DEBUG
|
+static void
|
+static void
|
+zip_debug_machine(MACHINEREGS *pzipm) {
|
+zip_debug_machine(MACHINEREGS *pzipm) {
|
+ int i;
|
+ int i;
|
+ for(i=0; i<ZIP_USER_REGS; i++) {
|
+ for(i=0; i<ZIP_USER_REGS; i++) {
|
Line 2360... |
Line 2411... |
+ case ZIPO_SDUMP: fprintf(stderr, "%7s", "SDUMP"); break;
|
+ case ZIPO_SDUMP: fprintf(stderr, "%7s", "SDUMP"); break;
|
+ case ZIPO_SEXIT: fprintf(stderr, "%7s", "SEXIT"); break;
|
+ case ZIPO_SEXIT: fprintf(stderr, "%7s", "SEXIT"); break;
|
+ case ZIPO_SOUT: fprintf(stderr, "%7s", "SOUT"); break;
|
+ case ZIPO_SOUT: fprintf(stderr, "%7s", "SOUT"); break;
|
+ case ZIPO_NDUMP: fprintf(stderr, "%7s", "NDUMP"); break;
|
+ case ZIPO_NDUMP: fprintf(stderr, "%7s", "NDUMP"); break;
|
+ case ZIPO_NEXIT: fprintf(stderr, "%7s", "NEXIT"); break;
|
+ case ZIPO_NEXIT: fprintf(stderr, "%7s", "NEXIT"); break;
|
+ case ZIPO_NOUT: fprintf(stderr, "%7s", "OUT"); break;
|
+ case ZIPO_NOUT: fprintf(stderr, "%7s", "NOUT"); break;
|
+ //
|
+ //
|
+ case ZIPO_LJMP: fprintf(stderr, "%7s", "LJMP"); break;
|
+ case ZIPO_LJMP: fprintf(stderr, "%7s", "LJMP"); break;
|
+ case ZIPO_LJSR: fprintf(stderr, "%7s", "LJSR"); break;
|
+ case ZIPO_LJSR: fprintf(stderr, "%7s", "LJSR"); break;
|
+ //
|
+ //
|
+ case ZIPO_SEXTH:fprintf(stderr, "%7s", "SEXTH"); break;
|
+ case ZIPO_SEXTH:fprintf(stderr, "%7s", "SEXTH"); break;
|
Line 2844... |
Line 2895... |
+ }
|
+ }
|
+
|
+
|
+ return err;
|
+ return err;
|
+}
|
+}
|
+
|
+
|
+static int fits_within(int nbits, int value) {
|
|
+ // -2 fits_within two bits
|
|
+ // -1 fits_within two bits
|
|
+ // 1 fits_within two bits
|
|
+ // 2 does not
|
|
+ //
|
|
+ if (value > 0)
|
|
+ return (value < (1l<<(nbits-1))) ? 1:0;
|
|
+ else
|
|
+ return (value >= -(1l<<(nbits-1))) ? 1:0;
|
|
+}
|
|
+
|
|
+static const char *zip_parse(const char *line, ZIPIS *insn) {
|
+static const char *zip_parse(const char *line, ZIPIS *insn) {
|
+ const char *err = NULL, *opstr = NULL;
|
+ const char *err = NULL, *opstr = NULL;
|
+ char *alt;
|
+ char *alt;
|
+ int i;
|
+ int i;
|
+ char *cndp = NULL;
|
+ char *cndp = NULL;
|
Line 2886... |
Line 2925... |
+ FORMTYPE insn_form = ILLEGAL_FORM; // Make sure we set this
|
+ FORMTYPE insn_form = ILLEGAL_FORM; // Make sure we set this
|
+
|
+
|
+
|
+
|
+
|
+
|
+#ifdef ZIP_DEBUG
|
+#ifdef ZIP_DEBUG
|
+ fprintf(stderr, "**** Parsing %s\n", line);
|
+ fprintf(stderr, "\n**** Parsing %s\n", line);
|
+#endif
|
+#endif
|
+
|
+
|
+ insn->i_naux = 0;
|
+ insn->i_naux = 0;
|
+ insn->i_op = ZIPO_NOOP;
|
+ insn->i_op = ZIPO_NOOP;
|
+ insn->i_cnd = ZIPC_ALWAYS;
|
+ insn->i_cnd = ZIPC_ALWAYS;
|
Line 3396... |
Line 3435... |
+ err = "Relocations not applicable for floating point ops";
|
+ err = "Relocations not applicable for floating point ops";
|
+ break;
|
+ break;
|
+ case ZIPO_TRAP:
|
+ case ZIPO_TRAP:
|
+ insn->i_areg = ZIP_CC;
|
+ insn->i_areg = ZIP_CC;
|
+ if (insn->i_breg == ZIP_RNONE) {
|
+ if (insn->i_breg == ZIP_RNONE) {
|
|
+ // TRAP instructions *ALWAYS* clear the GIE bit
|
|
+ insn->i_imm &= (~0x0020);
|
+ if (insn->i_cnd == ZIPC_ALWAYS)
|
+ if (insn->i_cnd == ZIPC_ALWAYS)
|
+ insn->i_op = ZIPO_LDI;
|
+ insn->i_op = ZIPO_LDI;
|
+ else if (fits_within(16, insn->i_imm))
|
+ else if (fits_within(16, insn->i_imm))
|
+ insn->i_op = ZIPO_LDILO;
|
+ insn->i_op = ZIPO_LDILO;
|
+ else if (fits_within(18, zip_brev(insn->i_imm)))
|
+ else if (fits_within(18, zip_brev(insn->i_imm)))
|
+ insn->i_op = ZIPO_BREV;
|
+ insn->i_op = ZIPO_BREV;
|
+ else
|
+ else
|
+ err = "TRAP immediate not supported";
|
+ err = "TRAP 18+ bit immediate not supported";
|
+ } else
|
+ } else
|
+ insn->i_op = ZIPO_MOV;
|
+ insn->i_op = ZIPO_MOV;
|
+ break;
|
+ break;
|
+ case ZIPO_CLR:
|
+ case ZIPO_CLR:
|
+ insn->i_op = ZIPO_LDI;
|
+ insn->i_op = ZIPO_LDI;
|
Line 3604... |
Line 3645... |
+ return 0;
|
+ return 0;
|
+
|
+
|
+ // 1. Can't merge anything that's already merged
|
+ // 1. Can't merge anything that's already merged
|
+ if ((a|b) & 0x80000000)
|
+ if ((a|b) & 0x80000000)
|
+ return 0;
|
+ return 0;
|
|
+
|
+ ZIP_OPCODE opa, opb;
|
+ ZIP_OPCODE opa, opb;
|
+ ZIP_CONDITION ac, bc;
|
+ ZIP_CONDITION ac, bc;
|
+ int imma, immb;
|
+ int imma, immb;
|
+
|
+
|
+ // Get the 5-bit operands for each
|
+ // Get the 5-bit operands for each
|
Line 3638... |
Line 3680... |
+ default:
|
+ default:
|
+ return 0;
|
+ return 0;
|
+ }
|
+ }
|
+
|
+
|
+ // Prohibit moves to/from user regs to merge
|
+ // Prohibit moves to/from user regs to merge
|
+ if ((opa == ZIPO_MOV)&&(a & 0x44000))
|
+ if ((opa == ZIPO_MOV)&&(a & 0x42000))
|
+ return 0;
|
+ return 0;
|
+ if ((opb == ZIPO_MOV)&&(b & 0x44000))
|
+ if ((opb == ZIPO_MOV)&&(b & 0x42000))
|
+ return 0;
|
+ return 0;
|
+
|
+
|
+ imma = zip_non_cis_immediate(a);
|
+ imma = zip_non_cis_immediate(a);
|
+ immb = zip_non_cis_immediate(b);
|
+ immb = zip_non_cis_immediate(b);
|
+
|
+
|
+ if (!fits_within(8,imma)) {
|
+ if (!fits_within(8,imma)) {
|
+ // fprintf(stderr, "As immediate is out of range\n");
|
|
+ return 0;
|
+ return 0;
|
+ } if (!fits_within(8,immb)) {
|
+ } if (!fits_within(8,immb)) {
|
+ // fprintf(stderr, "Bs immediate is out of range\n");
|
|
+ return 0;
|
+ return 0;
|
+ }
|
+ }
|
+
|
+
|
+ // if abreg & 0x010, or bbreg & 0x010, then the register is being
|
+ // if abreg & 0x010, or bbreg & 0x010, then the register is being
|
+ // used.
|
+ // used.
|
Line 3977... |
Line 4017... |
+ fprintf(stderr, "SYM-DEF %d,%d,%d,%d, IMM = %08x\n",
|
+ fprintf(stderr, "SYM-DEF %d,%d,%d,%d, IMM = %08x\n",
|
+ sym_defined, sym_known,
|
+ sym_defined, sym_known,
|
+ (insn->i_rp)&&(symbol_get_frag(insn->i_rp->r_sym)==fragP)?1:0,
|
+ (insn->i_rp)&&(symbol_get_frag(insn->i_rp->r_sym)==fragP)?1:0,
|
+ this_segment, insn->i_imm);
|
+ this_segment, insn->i_imm);
|
+#endif
|
+#endif
|
|
+ int rg;
|
|
+
|
+ switch(insn->i_op) {
|
+ switch(insn->i_op) {
|
+ case ZIPO_LDI: // May or may not be conditional
|
+ case ZIPO_LDI: // May or may not be conditional
|
+ if ((sym_known)&&(this_segment)
|
+ if ((sym_known)&&(this_segment)
|
+ &&(fits_within(15,immv+symv-fragP->fr_address-insn->i_rp->r_fr_offset-sizeof(uint32_t)))) {
|
+ &&(fits_within(15,immv+symv-fragP->fr_address-insn->i_rp->r_fr_offset-sizeof(uint32_t)))) {
|
+ // Turn this into a MOV x(PC),Rx
|
+ // Turn this into a MOV x(PC),Rx
|
Line 4000... |
Line 4042... |
+ }
|
+ }
|
+
|
+
|
+ // 0.111.x111.11
|
+ // 0.111.x111.11
|
+ insn->i_aux[0] = 0x7fc00000; // NOOP -- if never used.
|
+ insn->i_aux[0] = 0x7fc00000; // NOOP -- if never used.
|
+ immv += symv;
|
+ immv += symv;
|
|
+ if ((insn->i_cnd == ZIPC_ALWAYS)
|
|
+ &&(zip_param_cis)
|
|
+ &&(zip_param_use_machine)&&(pzipm)
|
|
+ &&(!fits_within(8,immv))) {
|
|
+ // Convert an LDI instruction to a MOV instruction if
|
|
+ // it would make that instruction CIS-able.
|
|
+
|
|
+ if ((rg=zip_findnearreg_machine(pzipm, immv))
|
|
+ != ZIP_RNONE) {
|
|
+ int d;
|
|
+ d = immv - pzipm->r[rg].m_value;
|
|
+ if (fits_within(3,d)) {
|
|
+ insn->i_op = ZIPO_MOV;
|
|
+ insn->i_breg = rg;
|
|
+ insn->i_naux = 0;
|
|
+ insn->i_imm = d;
|
|
+ zip_assemble_insn_words(fragP,
|
|
+ seg, insn, relax_state,
|
|
+ stretch, pzipm);
|
|
+ return;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
+ if ((!insn->i_rp)&&(insn->i_cnd == ZIPC_ALWAYS)
|
+ if ((!insn->i_rp)&&(insn->i_cnd == ZIPC_ALWAYS)
|
+ &&(fits_within(23, immv))) {
|
+ &&(fits_within(23, immv))) {
|
|
+ // Can we do this with an ordinary load immediate
|
|
+ // instruction?
|
|
+ //
|
|
+ // If we do this, we'll avoid any opportunity to use
|
|
+ // the ZipMachine and move something into this address
|
+ insn->i_naux = 0;
|
+ insn->i_naux = 0;
|
+ insn->i_code = LDIOP(immv,insn->i_areg);
|
+ insn->i_code = LDIOP(immv,insn->i_areg);
|
+ } else if (((!insn->i_rp)||(sym_known))
|
+ } else if (((!insn->i_rp)||(sym_known))
|
+ &&(fits_within(18, zip_brev(immv)))) {
|
+ &&(fits_within(18, zip_brev(immv)))) {
|
+ // Can we do this with a BREV instruction using an
|
+ // Can we do this with a BREV instruction using an
|
Line 4017... |
Line 4088... |
+ zip_brev(immv),
|
+ zip_brev(immv),
|
+ insn->i_areg&0x0f);
|
+ insn->i_areg&0x0f);
|
+ if (insn->i_rp)
|
+ if (insn->i_rp)
|
+ insn->i_rp->r_type = BFD_RELOC_NONE;
|
+ insn->i_rp->r_type = BFD_RELOC_NONE;
|
+// 0000 1110 0000 0000 0000 0000 0100 0000
|
+// 0000 1110 0000 0000 0000 0000 0100 0000
|
+ } else if ((zip_param_use_machine)&&(pzipm)&&((!insn->i_rp)||(sym_known))
|
+ } else if ((zip_param_use_machine)&&(pzipm)
|
|
+ &&((!insn->i_rp)||(sym_known))
|
+ &&(pzipm->r[insn->i_areg].m_known)
|
+ &&(pzipm->r[insn->i_areg].m_known)
|
+ &&(0==((immv^pzipm->r[insn->i_areg].m_value)
|
+ &&(0==((immv^pzipm->r[insn->i_areg].m_value)
|
+ & 0x0ffff0000))) {
|
+ & 0x0ffff0000))) {
|
+ // Replace LDI with LDILO
|
+ // Replace LDI with LDILO
|
+ insn->i_naux = 0;
|
+ insn->i_naux = 0;
|
Line 4033... |
Line 4105... |
+ // Henceforth, we only know the bottom 16bits
|
+ // Henceforth, we only know the bottom 16bits
|
+ // of this register
|
+ // of this register
|
+ pzipm->r[insn->i_areg].m_known = MACH_VUPPERKNOWN;
|
+ pzipm->r[insn->i_areg].m_known = MACH_VUPPERKNOWN;
|
+ } else
|
+ } else
|
+ pzipm->r[insn->i_areg].m_known = MACH_VKNOWN;
|
+ pzipm->r[insn->i_areg].m_known = MACH_VKNOWN;
|
|
+ } else if ((zip_param_use_machine)&&(pzipm)
|
|
+ &&((!insn->i_rp)||(sym_known))
|
|
+ &&(pzipm->r[insn->i_areg].m_known)
|
|
+ &&((rg=zip_findnearreg_machine(pzipm, immv))!= ZIP_RNONE)
|
|
+ &&(fits_within(13,pzipm->r[rg].m_value - immv))) {
|
|
+ // Replace LDI with a MOV instruction
|
|
+ insn->i_op = ZIPO_MOV;
|
|
+ insn->i_breg = rg;
|
|
+ insn->i_naux = 0;
|
|
+ insn->i_imm = pzipm->r[rg].m_value - immv;
|
|
+ zip_assemble_insn_words(fragP, seg, insn,
|
|
+ relax_state, stretch, pzipm);
|
|
+ return;
|
|
+ } else if ((zip_param_use_machine)&&(pzipm)
|
|
+ &&((!insn->i_rp)||(sym_known))
|
|
+ &&(pzipm->r[insn->i_areg].m_known)
|
|
+ &&((rg=zip_findnearreg_machine(pzipm, zip_brev(immv)))!= ZIP_RNONE)
|
|
+ &&(fits_within(14,zip_brev(pzipm->r[rg].m_value - immv)))) {
|
|
+ // Replace LDI with a MOV instruction
|
|
+ insn->i_op = ZIPO_BREV;
|
|
+ insn->i_breg = rg;
|
|
+ insn->i_naux = 0;
|
|
+ insn->i_imm = zip_brev(pzipm->r[rg].m_value - immv);
|
|
+ zip_assemble_insn_words(fragP, seg, insn,
|
|
+ relax_state, stretch, pzipm);
|
|
+ return;
|
+ } else {
|
+ } else {
|
+ //
|
+ //
|
+ // If the symbol isn't defined, then any immv value
|
+ // If the symbol isn't defined, then any immv value
|
+ // will work--we have to come back anyway.
|
+ // will work--we have to come back anyway.
|
+ //
|
+ //
|
+ int known_bypass = 0, i;
|
|
+
|
|
+ if ((zip_param_use_machine)&&(pzipm)&&(
|
|
+ ((!insn->i_rp)
|
|
+ &&(!fits_within(4,immv)))
|
|
+ ||((insn->i_rp)&&(sym_known)))) {
|
|
+ for(i=0; i<14; i++) {
|
|
+ int offset = immv-pzipm->r[i].m_value;
|
|
+ if ((pzipm->r[i].m_known==MACH_VKNOWN)
|
|
+ &&(fits_within(13, offset))
|
|
+ &&((insn->i_rp)
|
|
+ ||(!fits_within(4, immv)))
|
|
+ ) {
|
|
+ // Pick the closest value ... if
|
|
+ // there's a choice
|
|
+ if ((!known_bypass)
|
|
+ ||(abs(offset)<known_bypass))
|
|
+ continue;
|
|
+ insn->i_naux = 0;
|
|
+ insn->i_op = ZIPO_MOV;
|
|
+ insn->i_breg = i;
|
|
+ insn->i_imm = offset;
|
|
+
|
|
+ insn->i_code = SMPLMOV(
|
|
+ insn->i_cnd, offset,
|
|
+ i, insn->i_areg);
|
|
+ known_bypass = abs(offset);
|
|
+ if (known_bypass==0)
|
|
+ known_bypass = 1;
|
|
+ }
|
|
+ } known_bypass = (known_bypass)?1:0;
|
|
+ } if (!known_bypass) {
|
|
+ // BREV Extension would modify this statement
|
+ // BREV Extension would modify this statement
|
+ insn->i_naux = 1;
|
+ insn->i_naux = 1;
|
+ insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
|
+ insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
|
+ zip_brev(immv)&0x01ffff, insn->i_areg);
|
+ zip_brev(immv)&0x01ffff, insn->i_areg);
|
+ insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd,
|
+ insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd,
|
Line 4082... |
Line 4148... |
+ insn->i_rp->r_type = BFD_RELOC_ZIP_LDI;
|
+ insn->i_rp->r_type = BFD_RELOC_ZIP_LDI;
|
+ else if ((zip_param_cis)&&(zip_can_merge(insn->i_code, insn->i_aux[0]))) {
|
+ else if ((zip_param_cis)&&(zip_can_merge(insn->i_code, insn->i_aux[0]))) {
|
+ insn->i_code = zip_insn_merge(insn->i_code, insn->i_aux[0]);
|
+ insn->i_code = zip_insn_merge(insn->i_code, insn->i_aux[0]);
|
+ insn->i_naux = 0;
|
+ insn->i_naux = 0;
|
+ }
|
+ }
|
+ } else {
|
|
+fprintf(stderr, "known-bypass\n");
|
|
+ }
|
|
+ }
|
+ }
|
+#ifdef ZIP_DEBUG
|
+#ifdef ZIP_DEBUG
|
+ fprintf(stderr, "LDI %04x:%04x,%d Instruction assembled into %08x : %08x\n",
|
+ fprintf(stderr, "LDI %04x:%04x,%d Instruction assembled into %08x : %08x\n",
|
+ (immv>>16)&0x0ffff,
|
+ (immv>>16)&0x0ffff,
|
+ immv & 0x0ffff, insn->i_areg,
|
+ immv & 0x0ffff, insn->i_areg,
|
Line 5045... |
Line 5108... |
+ insn->i_rp->r_pcrel, // T if PC-Relative reloc
|
+ insn->i_rp->r_pcrel, // T if PC-Relative reloc
|
+ insn->i_rp->r_type); // Reloc type
|
+ insn->i_rp->r_type); // Reloc type
|
+ }
|
+ }
|
+ }
|
+ }
|
+}
|
+}
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.h binutils-2.27-zip/gas/config/tc-zip.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/config/tc-zip.h binutils-2.27-zip/gas/config/tc-zip.h
|
--- binutils-2.27/gas/config/tc-zip.h 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/config/tc-zip.h 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/config/tc-zip.h 2017-03-03 09:35:34.527310651 -0500
|
+++ binutils-2.27-zip/gas/config/tc-zip.h 2017-03-03 09:35:34.527310651 -0500
|
@@ -0,0 +1,191 @@
|
@@ -0,0 +1,191 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: tc-zip.h
|
+// Filename: tc-zip.h
|
Line 5240... |
Line 5303... |
+ ZIPV_LW, ZIPV_SW, ZIPV_LDI, ZIPV_MOV, // 3'h1xx
|
+ ZIPV_LW, ZIPV_SW, ZIPV_LDI, ZIPV_MOV, // 3'h1xx
|
+} ZIP_VLIWCODE;
|
+} ZIP_VLIWCODE;
|
+
|
+
|
+#endif
|
+#endif
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/configure.tgt binutils-2.27-zip/gas/configure.tgt
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/configure.tgt binutils-2.27-zip/gas/configure.tgt
|
--- binutils-2.27/gas/configure.tgt 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/gas/configure.tgt 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/gas/configure.tgt 2016-12-31 17:44:37.270167826 -0500
|
+++ binutils-2.27-zip/gas/configure.tgt 2016-12-31 17:44:37.270167826 -0500
|
@@ -112,6 +112,7 @@
|
@@ -112,6 +112,7 @@
|
x86_64*) cpu_type=i386 arch=x86_64;;
|
x86_64*) cpu_type=i386 arch=x86_64;;
|
xgate) cpu_type=xgate ;;
|
xgate) cpu_type=xgate ;;
|
xtensa*) cpu_type=xtensa arch=xtensa ;;
|
xtensa*) cpu_type=xtensa arch=xtensa ;;
|
Line 5260... |
Line 5323... |
+ zip*) fmt=elf ;;
|
+ zip*) fmt=elf ;;
|
+
|
+
|
*-*-aout | *-*-scout) fmt=aout ;;
|
*-*-aout | *-*-scout) fmt=aout ;;
|
*-*-cloudabi*) fmt=elf ;;
|
*-*-cloudabi*) fmt=elf ;;
|
*-*-dragonfly*) fmt=elf em=dragonfly ;;
|
*-*-dragonfly*) fmt=elf em=dragonfly ;;
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.am binutils-2.27-zip/gas/Makefile.am
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/Makefile.am binutils-2.27-zip/gas/Makefile.am
|
--- binutils-2.27/gas/Makefile.am 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/gas/Makefile.am 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/gas/Makefile.am 2016-12-31 17:45:17.941851449 -0500
|
+++ binutils-2.27-zip/gas/Makefile.am 2016-12-31 17:45:17.941851449 -0500
|
@@ -200,6 +200,7 @@
|
@@ -200,6 +200,7 @@
|
config/tc-xtensa.c \
|
config/tc-xtensa.c \
|
config/tc-z80.c \
|
config/tc-z80.c \
|
config/tc-z8k.c \
|
config/tc-z8k.c \
|
Line 5279... |
Line 5342... |
config/tc-z8k.h \
|
config/tc-z8k.h \
|
+ config/tc-zip.h \
|
+ config/tc-zip.h \
|
config/xtensa-relax.h
|
config/xtensa-relax.h
|
|
|
# OBJ files in config
|
# OBJ files in config
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.in binutils-2.27-zip/gas/Makefile.in
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/Makefile.in binutils-2.27-zip/gas/Makefile.in
|
--- binutils-2.27/gas/Makefile.in 2016-08-03 04:16:28.000000000 -0400
|
--- binutils-2.27-original/gas/Makefile.in 2016-08-03 04:16:28.000000000 -0400
|
+++ binutils-2.27-zip/gas/Makefile.in 2016-12-31 17:49:43.603837948 -0500
|
+++ binutils-2.27-zip/gas/Makefile.in 2016-12-31 17:49:43.603837948 -0500
|
@@ -494,6 +494,7 @@
|
@@ -494,6 +494,7 @@
|
config/tc-xtensa.c \
|
config/tc-xtensa.c \
|
config/tc-z80.c \
|
config/tc-z80.c \
|
config/tc-z8k.c \
|
config/tc-z8k.c \
|
Line 5327... |
Line 5390... |
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-zip.obj `if test -f 'config/tc-zip.c'; then $(CYGPATH_W) 'config/tc-zip.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-zip.c'; fi`
|
+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-zip.obj `if test -f 'config/tc-zip.c'; then $(CYGPATH_W) 'config/tc-zip.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-zip.c'; fi`
|
+
|
+
|
xtensa-relax.o: config/xtensa-relax.c
|
xtensa-relax.o: config/xtensa-relax.c
|
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa-relax.o -MD -MP -MF $(DEPDIR)/xtensa-relax.Tpo -c -o xtensa-relax.o `test -f 'config/xtensa-relax.c' || echo '$(srcdir)/'`config/xtensa-relax.c
|
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa-relax.o -MD -MP -MF $(DEPDIR)/xtensa-relax.Tpo -c -o xtensa-relax.o `test -f 'config/xtensa-relax.c' || echo '$(srcdir)/'`config/xtensa-relax.c
|
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/xtensa-relax.Tpo $(DEPDIR)/xtensa-relax.Po
|
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/xtensa-relax.Tpo $(DEPDIR)/xtensa-relax.Po
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip.exp binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip.exp binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp
|
--- binutils-2.27/gas/testsuite/gas/zip/zip.exp 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip.exp 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp 2017-01-12 22:12:40.839206088 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp 2017-01-12 22:12:40.839206088 -0500
|
@@ -0,0 +1,17 @@
|
@@ -0,0 +1,17 @@
|
+# ZipCPU assembler testsuite
|
+# ZipCPU assembler testsuite
|
+
|
+
|
+if [istarget zip*] {
|
+if [istarget zip*] {
|
Line 5348... |
Line 5411... |
+ run_dump_test "zip_insn_vliw"
|
+ run_dump_test "zip_insn_vliw"
|
+ # run_dump_test "zip_insn_fpu"
|
+ # run_dump_test "zip_insn_fpu"
|
+ # run_dump_test "zip_insn_jsr"
|
+ # run_dump_test "zip_insn_jsr"
|
+ # run_dump_test "zip_insn_jsrv"
|
+ # run_dump_test "zip_insn_jsrv"
|
+}
|
+}
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d 2017-01-12 22:01:30.790982203 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d 2017-01-12 22:01:30.790982203 -0500
|
@@ -0,0 +1,41 @@
|
@@ -0,0 +1,41 @@
|
+#as: -novliw
|
+#as: -novliw
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Generic OpB instruction test
|
+#name: Generic OpB instruction test
|
Line 5393... |
Line 5456... |
+ 68: 70 80 00 04 ADD +.4,CC
|
+ 68: 70 80 00 04 ADD +.4,CC
|
+ 6c: 78 80 00 04 BRA +@0x00000074.*$
|
+ 6c: 78 80 00 04 BRA +@0x00000074.*$
|
+ 70: 78 89 ff ff BZ +@0x00020073.*$
|
+ 70: 78 89 ff ff BZ +@0x00020073.*$
|
+ 74: 78 aa 00 00 BNZ +@0xfffe0078.*$
|
+ 74: 78 aa 00 00 BNZ +@0xfffe0078.*$
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s 2017-01-10 12:00:50.870044337 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s 2017-01-10 12:00:50.870044337 -0500
|
@@ -0,0 +1,33 @@
|
@@ -0,0 +1,33 @@
|
+ .text
|
+ .text
|
+
|
+
|
+add_insn_test:
|
+add_insn_test:
|
Line 5430... |
Line 5493... |
+ [v] add 4,sp
|
+ [v] add 4,sp
|
+ add 4,cc
|
+ add 4,cc
|
+ add 4,pc
|
+ add 4,pc
|
+ add.z 131071,pc
|
+ add.z 131071,pc
|
+ add.nz -131072,pc
|
+ add.nz -131072,pc
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d 2017-01-10 10:46:16.957469423 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d 2017-01-10 10:46:16.957469423 -0500
|
@@ -0,0 +1,22 @@
|
@@ -0,0 +1,22 @@
|
+#as:
|
+#as:
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Local branch (BRA) and conditional branch testing
|
+#name: Local branch (BRA) and conditional branch testing
|
Line 5456... |
Line 5519... |
+ 1c: 78 a0 00 04 BV @0x00000024 // .. <bra_target>
|
+ 1c: 78 a0 00 04 BV @0x00000024 // .. <bra_target>
|
+ 20: 06 7f ff ff LDI \$-1,R0
|
+ 20: 06 7f ff ff LDI \$-1,R0
|
+
|
+
|
+00000024 <bra_target>:
|
+00000024 <bra_target>:
|
+ 24: 7f c0 00 00 NOOP
|
+ 24: 7f c0 00 00 NOOP
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s 2017-01-09 10:28:54.983992877 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s 2017-01-09 10:28:54.983992877 -0500
|
@@ -0,0 +1,14 @@
|
@@ -0,0 +1,14 @@
|
+ .text
|
+ .text
|
+
|
+
|
+bra_insn_test:
|
+bra_insn_test:
|
Line 5474... |
Line 5537... |
+ bge bra_target
|
+ bge bra_target
|
+ bv bra_target
|
+ bv bra_target
|
+ ldi -1,r0
|
+ ldi -1,r0
|
+bra_target:
|
+bra_target:
|
+ noop
|
+ noop
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d 2017-01-16 11:02:02.344009430 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d 2017-01-16 11:02:02.344009430 -0500
|
@@ -0,0 +1,39 @@
|
@@ -0,0 +1,39 @@
|
+#as:
|
+#as:
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Conditional predicate test(s)
|
+#name: Conditional predicate test(s)
|
Line 5517... |
Line 5580... |
+ 60: 00 a0 00 01 ADD.V +\$1,R0
|
+ 60: 00 a0 00 01 ADD.V +\$1,R0
|
+ 64: 00 98 00 01 ADD.C +\$1,R0
|
+ 64: 00 98 00 01 ADD.C +\$1,R0
|
+ 68: 00 98 00 01 ADD.C +\$1,R0
|
+ 68: 00 98 00 01 ADD.C +\$1,R0
|
+ 6c: 00 b8 00 01 ADD.NC +\$1,R0
|
+ 6c: 00 b8 00 01 ADD.NC +\$1,R0
|
+ 70: 00 b8 00 01 ADD.NC +\$1,R0
|
+ 70: 00 b8 00 01 ADD.NC +\$1,R0
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s 2017-01-16 10:55:53.054697861 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s 2017-01-16 10:55:53.054697861 -0500
|
@@ -0,0 +1,34 @@
|
@@ -0,0 +1,34 @@
|
+ .text
|
+ .text
|
+
|
+
|
+conditional_tests:
|
+conditional_tests:
|
Line 5555... |
Line 5618... |
+ [c] add 1,R0
|
+ [c] add 1,R0
|
+ [ltu] add 1,R0
|
+ [ltu] add 1,R0
|
+ [nc] add 1,R0
|
+ [nc] add 1,R0
|
+ [geu] add 1,R0
|
+ [geu] add 1,R0
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d 2017-01-10 11:31:45.633275455 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d 2017-01-10 11:31:45.633275455 -0500
|
@@ -0,0 +1,24 @@
|
@@ -0,0 +1,24 @@
|
+#as: -nozipm
|
+#as: -nozipm
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Load-Immediate test
|
+#name: Load-Immediate test
|
Line 5583... |
Line 5646... |
+ 24: 32 40 00 01
|
+ 24: 32 40 00 01
|
+ 28: 3a 00 01 ff BREV +\$511,R7
|
+ 28: 3a 00 01 ff BREV +\$511,R7
|
+ 2c: 42 03 fe ff BREV +\$-257,R8
|
+ 2c: 42 03 fe ff BREV +\$-257,R8
|
+ 30: 4a 01 fe ff LDI +0xff7ffffe,R9.*
|
+ 30: 4a 01 fe ff LDI +0xff7ffffe,R9.*
|
+ 34: 4a 40 ff fe
|
+ 34: 4a 40 ff fe
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s 2017-01-09 10:28:37.472119620 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s 2017-01-09 10:28:37.472119620 -0500
|
@@ -0,0 +1,13 @@
|
@@ -0,0 +1,13 @@
|
+ .text
|
+ .text
|
+
|
+
|
+ldi_insn_test:
|
+ldi_insn_test:
|
Line 5600... |
Line 5663... |
+ ldi 8388607,r5
|
+ ldi 8388607,r5
|
+ ldi -8388607,r6
|
+ ldi -8388607,r6
|
+ ldi -8388608,r7
|
+ ldi -8388608,r7
|
+ ldi -8388609,r8
|
+ ldi -8388609,r8
|
+ ldi -8388610,r9
|
+ ldi -8388610,r9
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d 2017-01-12 22:09:54.925246052 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d 2017-01-12 22:09:54.925246052 -0500
|
@@ -0,0 +1,86 @@
|
@@ -0,0 +1,86 @@
|
+#as: -novliw -nozipm
|
+#as: -novliw -nozipm
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Mov instruction special test
|
+#name: Mov instruction special test
|
Line 5690... |
Line 5753... |
+000000c0 <move_to_cc>:
|
+000000c0 <move_to_cc>:
|
+ c0: 73 40 10 00 MOV +\$-4096\+R0,CC
|
+ c0: 73 40 10 00 MOV +\$-4096\+R0,CC
|
+ c4: 73 40 90 01 MOV +\$-4095\+R2,CC
|
+ c4: 73 40 90 01 MOV +\$-4095\+R2,CC
|
+ c8: 73 41 0f ff MOV +\$4095\+R4,CC
|
+ c8: 73 41 0f ff MOV +\$4095\+R4,CC
|
+ cc: 73 41 80 00 MOV +R6,CC
|
+ cc: 73 41 80 00 MOV +R6,CC
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s 2017-01-12 16:45:17.027962005 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s 2017-01-12 16:45:17.027962005 -0500
|
@@ -0,0 +1,93 @@
|
@@ -0,0 +1,93 @@
|
+ .text
|
+ .text
|
+
|
+
|
+mov_insn_test:
|
+mov_insn_test:
|
Line 5787... |
Line 5850... |
+ mov -4096+r0,cc
|
+ mov -4096+r0,cc
|
+ mov -4095+r2,cc
|
+ mov -4095+r2,cc
|
+ mov 4095+r4,cc
|
+ mov 4095+r4,cc
|
+ mov r6,cc
|
+ mov r6,cc
|
+ ;
|
+ ;
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d 2017-01-12 22:12:11.497444662 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d 2017-01-12 22:12:11.497444662 -0500
|
@@ -0,0 +1,98 @@
|
@@ -0,0 +1,98 @@
|
+#as: -novliw -nozipm
|
+#as: -novliw -nozipm
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: OpCode generation test
|
+#name: OpCode generation test
|
Line 5889... |
Line 5952... |
+ 14c: 1d 02 00 00 LH +\(\$-131072\),R3
|
+ 14c: 1d 02 00 00 LH +\(\$-131072\),R3
|
+ 150: 25 42 00 00 SH +R4,\(\$-131072\)
|
+ 150: 25 42 00 00 SH +R4,\(\$-131072\)
|
+ 154: 2c 82 00 00 LW +\(\$-131072\),R5
|
+ 154: 2c 82 00 00 LW +\(\$-131072\),R5
|
+ 158: 34 c2 00 00 SW +R6,\(\$-131072\)
|
+ 158: 34 c2 00 00 SW +R6,\(\$-131072\)
|
+ 15c: 17 82 00 00 FPI2F +\$-131072,R2
|
+ 15c: 17 82 00 00 FPI2F +\$-131072,R2
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s 2017-01-12 16:28:47.212542071 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s 2017-01-12 16:28:47.212542071 -0500
|
@@ -0,0 +1,119 @@
|
@@ -0,0 +1,119 @@
|
+ .text
|
+ .text
|
+
|
+
|
+optest:
|
+optest:
|
Line 6012... |
Line 6075... |
+ lw -0x20000,r5
|
+ lw -0x20000,r5
|
+ sw r6,-0x20000
|
+ sw r6,-0x20000
|
+ ; ldi
|
+ ; ldi
|
+ fpi2f -0x20000,r2
|
+ fpi2f -0x20000,r2
|
+ ;
|
+ ;
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d 2017-01-10 11:09:36.301473902 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d 2017-01-10 11:09:36.301473902 -0500
|
@@ -0,0 +1,32 @@
|
@@ -0,0 +1,32 @@
|
+#as: -novliw
|
+#as: -novliw
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Prologue test - Non-thumb
|
+#name: Prologue test - Non-thumb
|
Line 6048... |
Line 6111... |
+ 44: 04 87 40 18 LW +24\(SP\),R0
|
+ 44: 04 87 40 18 LW +24\(SP\),R0
|
+ 48: 04 87 40 1c LW +28\(SP\),R0
|
+ 48: 04 87 40 1c LW +28\(SP\),R0
|
+ 4c: 04 87 40 20 LW +32\(SP\),R0
|
+ 4c: 04 87 40 20 LW +32\(SP\),R0
|
+ 50: 68 80 00 30 ADD +\$48,SP
|
+ 50: 68 80 00 30 ADD +\$48,SP
|
+ 54: 7b 40 00 00 RTN +
|
+ 54: 7b 40 00 00 RTN +
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s 2017-01-09 07:25:40.495644200 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s 2017-01-09 07:25:40.495644200 -0500
|
@@ -0,0 +1,24 @@
|
@@ -0,0 +1,24 @@
|
+some_function:
|
+some_function:
|
+ SUB 48,SP
|
+ SUB 48,SP
|
+ SW R0,(SP)
|
+ SW R0,(SP)
|
Line 6076... |
Line 6139... |
+ LW 28(SP),R0
|
+ LW 28(SP),R0
|
+ LW 32(SP),R0
|
+ LW 32(SP),R0
|
+ ADD 48,SP
|
+ ADD 48,SP
|
+ RETN
|
+ RETN
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d 2017-01-12 21:58:59.513900839 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d 2017-01-12 21:58:59.513900839 -0500
|
@@ -0,0 +1,21 @@
|
@@ -0,0 +1,21 @@
|
+#as: -nozipm -vliw
|
+#as: -nozipm -vliw
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Prologue test - thumb
|
+#name: Prologue test - thumb
|
Line 6101... |
Line 6164... |
+ 18: 84 04 84 08 LW +4\(SP\),R0 +| LW +8\(SP\),R0
|
+ 18: 84 04 84 08 LW +4\(SP\),R0 +| LW +8\(SP\),R0
|
+ 1c: 84 0c 84 10 LW +12\(SP\),R0 +| LW +16\(SP\),R0
|
+ 1c: 84 0c 84 10 LW +12\(SP\),R0 +| LW +16\(SP\),R0
|
+ 20: 84 14 84 18 LW +20\(SP\),R0 +| LW +24\(SP\),R0
|
+ 20: 84 14 84 18 LW +20\(SP\),R0 +| LW +24\(SP\),R0
|
+ 24: 84 1c 84 20 LW +28\(SP\),R0 +| LW +32\(SP\),R0
|
+ 24: 84 1c 84 20 LW +28\(SP\),R0 +| LW +32\(SP\),R0
|
+ 28: ea 30 ff 80 ADD +\$48,SP +| MOV +R0,PC
|
+ 28: ea 30 ff 80 ADD +\$48,SP +| MOV +R0,PC
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s 2017-01-10 11:29:18.612449601 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s 2017-01-10 11:29:18.612449601 -0500
|
@@ -0,0 +1,24 @@
|
@@ -0,0 +1,24 @@
|
+some_function:
|
+some_function:
|
+ SUB 48,SP
|
+ SUB 48,SP
|
+ SW R0,(SP)
|
+ SW R0,(SP)
|
Line 6129... |
Line 6192... |
+ LW 28(SP),R0
|
+ LW 28(SP),R0
|
+ LW 32(SP),R0
|
+ LW 32(SP),R0
|
+ ADD 48,SP
|
+ ADD 48,SP
|
+ RETN
|
+ RETN
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d 2017-01-24 08:03:32.892847657 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d 2017-01-24 08:03:32.892847657 -0500
|
@@ -0,0 +1,41 @@
|
@@ -0,0 +1,41 @@
|
+#as:
|
+#as:
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Special instruction(s) test
|
+#name: Special instruction(s) test
|
Line 6174... |
Line 6237... |
+ 68: 7f c0 04 62 NOUT \$98
|
+ 68: 7f c0 04 62 NOUT \$98
|
+ 6c: 7f 80 02 22 SOUT R2
|
+ 6c: 7f 80 02 22 SOUT R2
|
+ 70: 7f c0 02 27 NOUT R7
|
+ 70: 7f c0 02 27 NOUT R7
|
+ 74: 7f 80 02 33 SOUT uR3
|
+ 74: 7f 80 02 33 SOUT uR3
|
+ 78: 7f c0 02 38 NOUT uR8
|
+ 78: 7f c0 02 38 NOUT uR8
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s 2017-01-19 07:18:13.405003668 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s 2017-01-19 07:18:13.405003668 -0500
|
@@ -0,0 +1,35 @@
|
@@ -0,0 +1,35 @@
|
+ .text
|
+ .text
|
+
|
+
|
+specials_test:
|
+specials_test:
|
Line 6213... |
Line 6276... |
+ sout R2
|
+ sout R2
|
+ nout R7
|
+ nout R7
|
+ sout uR3
|
+ sout uR3
|
+ nout uR8
|
+ nout uR8
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.d 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d 2017-01-12 21:50:28.719237156 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d 2017-01-12 21:50:28.719237156 -0500
|
@@ -0,0 +1,77 @@
|
@@ -0,0 +1,77 @@
|
+#as: -vliw
|
+#as: -vliw
|
+#objdump: -dr
|
+#objdump: -dr
|
+#name: Thumb instruction set test
|
+#name: Thumb instruction set test
|
Line 6294... |
Line 6357... |
+ e8: 9f 89 c8 0e MOV +\$1\+R1,R3 +| SUB +\$14,R9 *$
|
+ e8: 9f 89 c8 0e MOV +\$1\+R1,R3 +| SUB +\$14,R9 *$
|
+ ec: 99 11 aa 13 AND +\$17,R3 +| ADD +\$19,R5 *$
|
+ ec: 99 11 aa 13 AND +\$17,R3 +| ADD +\$19,R5 *$
|
+ f0: bb 3f c4 18 CMP +\$63\+R7,R7 +| LW 24\(SP\),R8 *$
|
+ f0: bb 3f c4 18 CMP +\$63\+R7,R7 +| LW 24\(SP\),R8 *$
|
+ f4: cd 1c de 7c SW +R9,\$28\(SP\) +| LDI +\$124,R11 *$
|
+ f4: cd 1c de 7c SW +R9,\$28\(SP\) +| LDI +\$124,R11 *$
|
+ f8: 1b 40 40 01 MOV +\$1\+R1,R3
|
+ f8: 1b 40 40 01 MOV +\$1\+R1,R3
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s
|
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.s 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s 2017-01-12 16:55:54.690241718 -0500
|
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s 2017-01-12 16:55:54.690241718 -0500
|
@@ -0,0 +1,110 @@
|
@@ -0,0 +1,110 @@
|
+ .text
|
+ .text
|
+
|
+
|
+vliw_merge_test:
|
+vliw_merge_test:
|
Line 6408... |
Line 6471... |
+ sw r9,28(sp)
|
+ sw r9,28(sp)
|
+ ldi 124,r11
|
+ ldi 124,r11
|
+ mov 1+r1,r3
|
+ mov 1+r1,r3
|
+
|
+
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/gas/write.c binutils-2.27-zip/gas/write.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/write.c binutils-2.27-zip/gas/write.c
|
--- binutils-2.27/gas/write.c 2016-08-03 03:36:51.000000000 -0400
|
--- binutils-2.27-original/gas/write.c 2016-08-03 03:36:51.000000000 -0400
|
+++ binutils-2.27-zip/gas/write.c 2016-12-31 17:51:52.470985149 -0500
|
+++ binutils-2.27-zip/gas/write.c 2016-12-31 17:51:52.470985149 -0500
|
@@ -2676,7 +2676,7 @@
|
@@ -2676,7 +2676,7 @@
|
|
|
case rs_org:
|
case rs_org:
|
{
|
{
|
- addressT target = offset;
|
- addressT target = offset;
|
+ addressT target = offset * OCTETS_PER_BYTE;
|
+ addressT target = offset * OCTETS_PER_BYTE;
|
addressT after;
|
addressT after;
|
|
|
if (symbolP)
|
if (symbolP)
|
diff -Naur '--exclude=*.swp' binutils-2.27/include/dis-asm.h binutils-2.27-zip/include/dis-asm.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/dis-asm.h binutils-2.27-zip/include/dis-asm.h
|
--- binutils-2.27/include/dis-asm.h 2016-08-03 03:36:53.000000000 -0400
|
--- binutils-2.27-original/include/dis-asm.h 2016-08-03 03:36:53.000000000 -0400
|
+++ binutils-2.27-zip/include/dis-asm.h 2016-12-31 17:52:29.022758231 -0500
|
+++ binutils-2.27-zip/include/dis-asm.h 2016-12-31 17:52:29.022758231 -0500
|
@@ -318,10 +318,12 @@
|
@@ -318,10 +318,12 @@
|
extern int print_insn_rl78_g10 (bfd_vma, disassemble_info *);
|
extern int print_insn_rl78_g10 (bfd_vma, disassemble_info *);
|
extern int print_insn_rl78_g13 (bfd_vma, disassemble_info *);
|
extern int print_insn_rl78_g13 (bfd_vma, disassemble_info *);
|
extern int print_insn_rl78_g14 (bfd_vma, disassemble_info *);
|
extern int print_insn_rl78_g14 (bfd_vma, disassemble_info *);
|
Line 6436... |
Line 6499... |
extern disassembler_ftype rl78_get_disassembler (bfd *);
|
extern disassembler_ftype rl78_get_disassembler (bfd *);
|
+extern disassembler_ftype zip_get_disassembler (bfd *);
|
+extern disassembler_ftype zip_get_disassembler (bfd *);
|
|
|
extern void print_aarch64_disassembler_options (FILE *);
|
extern void print_aarch64_disassembler_options (FILE *);
|
extern void print_i386_disassembler_options (FILE *);
|
extern void print_i386_disassembler_options (FILE *);
|
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/common.h binutils-2.27-zip/include/elf/common.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/elf/common.h binutils-2.27-zip/include/elf/common.h
|
--- binutils-2.27/include/elf/common.h 2016-08-03 03:36:53.000000000 -0400
|
--- binutils-2.27-original/include/elf/common.h 2016-08-03 03:36:53.000000000 -0400
|
+++ binutils-2.27-zip/include/elf/common.h 2016-12-31 17:53:58.942198950 -0500
|
+++ binutils-2.27-zip/include/elf/common.h 2016-12-31 17:53:58.942198950 -0500
|
@@ -411,6 +411,9 @@
|
@@ -411,6 +411,9 @@
|
/* Old constant that might be in use by some software. */
|
/* Old constant that might be in use by some software. */
|
#define EM_OPENRISC EM_OR1K
|
#define EM_OPENRISC EM_OR1K
|
|
|
Line 6449... |
Line 6512... |
+#define EM_ZIP 0xdad1
|
+#define EM_ZIP 0xdad1
|
+
|
+
|
/* See the above comment before you add a new EM_* value here. */
|
/* See the above comment before you add a new EM_* value here. */
|
|
|
/* Values for e_version. */
|
/* Values for e_version. */
|
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/zip.h binutils-2.27-zip/include/elf/zip.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/elf/zip.h binutils-2.27-zip/include/elf/zip.h
|
--- binutils-2.27/include/elf/zip.h 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/include/elf/zip.h 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/include/elf/zip.h 2017-01-18 18:19:33.764898333 -0500
|
+++ binutils-2.27-zip/include/elf/zip.h 2017-01-18 18:19:33.764898333 -0500
|
@@ -0,0 +1,58 @@
|
@@ -0,0 +1,58 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip.h
|
+// Filename: zip.h
|
Line 6511... |
Line 6574... |
+ // RELOC_NUMBER (R_ZIP_OPB_GOTREL, 11)
|
+ // RELOC_NUMBER (R_ZIP_OPB_GOTREL, 11)
|
+ // RELOC_NUMBER (R_ZIP_MOV_GOTREL, 12)
|
+ // RELOC_NUMBER (R_ZIP_MOV_GOTREL, 12)
|
+END_RELOC_NUMBERS(R_ZIP_max)
|
+END_RELOC_NUMBERS(R_ZIP_max)
|
+
|
+
|
+#endif /* _ELF_ZIP_H */
|
+#endif /* _ELF_ZIP_H */
|
diff -Naur '--exclude=*.swp' binutils-2.27/ld/configure.tgt binutils-2.27-zip/ld/configure.tgt
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/configure.tgt binutils-2.27-zip/ld/configure.tgt
|
--- binutils-2.27/ld/configure.tgt 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/ld/configure.tgt 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/ld/configure.tgt 2016-12-31 17:55:04.013793303 -0500
|
+++ binutils-2.27-zip/ld/configure.tgt 2016-12-31 17:55:04.013793303 -0500
|
@@ -816,6 +816,8 @@
|
@@ -816,6 +816,8 @@
|
;;
|
;;
|
z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001
|
z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001
|
;;
|
;;
|
+zip*) targ_emul=elf32zip;
|
+zip*) targ_emul=elf32zip;
|
+ ;;
|
+ ;;
|
*-*-ieee*) targ_emul=vanilla
|
*-*-ieee*) targ_emul=vanilla
|
;;
|
;;
|
*-tandem-none) targ_emul=st2000
|
*-tandem-none) targ_emul=st2000
|
diff -Naur '--exclude=*.swp' binutils-2.27/ld/emulparams/elf32zip.sh binutils-2.27-zip/ld/emulparams/elf32zip.sh
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/emulparams/elf32zip.sh binutils-2.27-zip/ld/emulparams/elf32zip.sh
|
--- binutils-2.27/ld/emulparams/elf32zip.sh 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/ld/emulparams/elf32zip.sh 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/ld/emulparams/elf32zip.sh 2017-01-05 08:22:45.000000000 -0500
|
+++ binutils-2.27-zip/ld/emulparams/elf32zip.sh 2017-01-05 08:22:45.000000000 -0500
|
@@ -0,0 +1,50 @@
|
@@ -0,0 +1,50 @@
|
+################################################################################
|
+################################################################################
|
+#
|
+#
|
+# Filename: elf32zip.sh
|
+# Filename: elf32zip.sh
|
Line 6577... |
Line 6640... |
+TEXT_START_ADDR="0x08000"
|
+TEXT_START_ADDR="0x08000"
|
+MAXPAGESIZE=0x01000
|
+MAXPAGESIZE=0x01000
|
+COMMONPAGESIZE=0x1000
|
+COMMONPAGESIZE=0x1000
|
+EMBEDDED=yes
|
+EMBEDDED=yes
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.am binutils-2.27-zip/ld/Makefile.am
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/Makefile.am binutils-2.27-zip/ld/Makefile.am
|
--- binutils-2.27/ld/Makefile.am 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/ld/Makefile.am 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/ld/Makefile.am 2016-12-31 17:57:39.684819835 -0500
|
+++ binutils-2.27-zip/ld/Makefile.am 2016-12-31 17:57:39.684819835 -0500
|
@@ -286,6 +286,7 @@
|
@@ -286,6 +286,7 @@
|
eelf32xc16xs.c \
|
eelf32xc16xs.c \
|
eelf32xstormy16.c \
|
eelf32xstormy16.c \
|
eelf32xtensa.c \
|
eelf32xtensa.c \
|
Line 6598... |
Line 6661... |
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
+
|
+
|
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
|
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
|
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
|
|
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.in binutils-2.27-zip/ld/Makefile.in
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/Makefile.in binutils-2.27-zip/ld/Makefile.in
|
--- binutils-2.27/ld/Makefile.in 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/ld/Makefile.in 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/ld/Makefile.in 2016-12-31 17:59:30.788122513 -0500
|
+++ binutils-2.27-zip/ld/Makefile.in 2016-12-31 17:59:30.788122513 -0500
|
@@ -654,6 +654,7 @@
|
@@ -654,6 +654,7 @@
|
eelf32xc16xs.c \
|
eelf32xc16xs.c \
|
eelf32xstormy16.c \
|
eelf32xstormy16.c \
|
eelf32xtensa.c \
|
eelf32xtensa.c \
|
Line 6627... |
Line 6690... |
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
+ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
+
|
+
|
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
|
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
|
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
|
|
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure binutils-2.27-zip/opcodes/configure
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/configure binutils-2.27-zip/opcodes/configure
|
--- binutils-2.27/opcodes/configure 2016-08-03 04:33:39.000000000 -0400
|
--- binutils-2.27-original/opcodes/configure 2016-08-03 04:33:39.000000000 -0400
|
+++ binutils-2.27-zip/opcodes/configure 2017-01-05 08:50:32.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/configure 2017-01-05 08:50:32.000000000 -0500
|
@@ -12685,7 +12685,7 @@
|
@@ -12685,7 +12685,7 @@
|
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
|
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
|
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
|
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
|
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
|
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
|
-
|
-
|
+ bfd_zip_arch) ta="$ta zip-dis.lo zip-opc.lo" ;;
|
+ bfd_zip_arch) ta="$ta zip-dis.lo zip-opc.lo" ;;
|
"") ;;
|
"") ;;
|
*) as_fn_error "*** unknown target architecture $arch" "$LINENO" 5 ;;
|
*) as_fn_error "*** unknown target architecture $arch" "$LINENO" 5 ;;
|
esac
|
esac
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure.ac binutils-2.27-zip/opcodes/configure.ac
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/configure.ac binutils-2.27-zip/opcodes/configure.ac
|
--- binutils-2.27/opcodes/configure.ac 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/opcodes/configure.ac 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/opcodes/configure.ac 2017-01-05 08:49:53.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/configure.ac 2017-01-05 08:49:53.000000000 -0500
|
@@ -353,7 +353,7 @@
|
@@ -353,7 +353,7 @@
|
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
|
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
|
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
|
bfd_z80_arch) ta="$ta z80-dis.lo" ;;
|
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
|
bfd_z8k_arch) ta="$ta z8k-dis.lo" ;;
|
-
|
-
|
+ bfd_zip_arch) ta="$ta zip-dis.lo zip-opc.lo" ;;
|
+ bfd_zip_arch) ta="$ta zip-dis.lo zip-opc.lo" ;;
|
"") ;;
|
"") ;;
|
*) AC_MSG_ERROR(*** unknown target architecture $arch) ;;
|
*) AC_MSG_ERROR(*** unknown target architecture $arch) ;;
|
esac
|
esac
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/disassemble.c binutils-2.27-zip/opcodes/disassemble.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/disassemble.c binutils-2.27-zip/opcodes/disassemble.c
|
--- binutils-2.27/opcodes/disassemble.c 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/opcodes/disassemble.c 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/opcodes/disassemble.c 2016-12-31 18:02:03.139162969 -0500
|
+++ binutils-2.27-zip/opcodes/disassemble.c 2016-12-31 18:02:03.139162969 -0500
|
@@ -98,6 +98,7 @@
|
@@ -98,6 +98,7 @@
|
#define ARCH_xtensa
|
#define ARCH_xtensa
|
#define ARCH_z80
|
#define ARCH_z80
|
#define ARCH_z8k
|
#define ARCH_z8k
|
Line 6674... |
Line 6737... |
+ break;
|
+ break;
|
+#endif
|
+#endif
|
#ifdef ARCH_vax
|
#ifdef ARCH_vax
|
case bfd_arch_vax:
|
case bfd_arch_vax:
|
disassemble = print_insn_vax;
|
disassemble = print_insn_vax;
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.am binutils-2.27-zip/opcodes/Makefile.am
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/Makefile.am binutils-2.27-zip/opcodes/Makefile.am
|
--- binutils-2.27/opcodes/Makefile.am 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/opcodes/Makefile.am 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/opcodes/Makefile.am 2017-01-05 08:28:32.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/Makefile.am 2017-01-05 08:28:32.000000000 -0500
|
@@ -86,7 +86,9 @@
|
@@ -86,7 +86,9 @@
|
w65-opc.h \
|
w65-opc.h \
|
xc16x-desc.h xc16x-opc.h \
|
xc16x-desc.h xc16x-opc.h \
|
xstormy16-desc.h xstormy16-opc.h \
|
xstormy16-desc.h xstormy16-opc.h \
|
Line 6707... |
Line 6770... |
libopcodes.a: stamp-lib ; @true
|
libopcodes.a: stamp-lib ; @true
|
-
|
-
|
POTFILES = $(HFILES) $(CFILES)
|
POTFILES = $(HFILES) $(CFILES)
|
po/POTFILES.in: @MAINT@ Makefile
|
po/POTFILES.in: @MAINT@ Makefile
|
for f in $(POTFILES); do echo $$f; done | LC_ALL=C sort > tmp \
|
for f in $(POTFILES); do echo $$f; done | LC_ALL=C sort > tmp \
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.in binutils-2.27-zip/opcodes/Makefile.in
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/Makefile.in binutils-2.27-zip/opcodes/Makefile.in
|
--- binutils-2.27/opcodes/Makefile.in 2016-08-03 03:36:54.000000000 -0400
|
--- binutils-2.27-original/opcodes/Makefile.in 2016-08-03 03:36:54.000000000 -0400
|
+++ binutils-2.27-zip/opcodes/Makefile.in 2017-01-05 08:28:04.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/Makefile.in 2017-01-05 08:28:04.000000000 -0500
|
@@ -386,7 +386,9 @@
|
@@ -386,7 +386,9 @@
|
w65-opc.h \
|
w65-opc.h \
|
xc16x-desc.h xc16x-opc.h \
|
xc16x-desc.h xc16x-opc.h \
|
xstormy16-desc.h xstormy16-opc.h \
|
xstormy16-desc.h xstormy16-opc.h \
|
Line 6741... |
Line 6804... |
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-dis.Plo@am__quote@
|
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-dis.Plo@am__quote@
|
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-opc.Plo@am__quote@
|
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-opc.Plo@am__quote@
|
|
|
.c.o:
|
.c.o:
|
@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
|
@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.c binutils-2.27-zip/opcodes/zip-dis.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-dis.c binutils-2.27-zip/opcodes/zip-dis.c
|
--- binutils-2.27/opcodes/zip-dis.c 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/opcodes/zip-dis.c 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/zip-dis.c 2017-03-03 09:34:03.983308793 -0500
|
+++ binutils-2.27-zip/opcodes/zip-dis.c 2018-03-22 17:57:34.688834861 -0400
|
@@ -0,0 +1,474 @@
|
@@ -0,0 +1,527 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-dis.c
|
+// Filename: zip-dis.c
|
+//
|
+//
|
+// Project: Zip CPU backend for GNU Binutils
|
+// Project: Zip CPU backend for GNU Binutils
|
Line 6834... |
Line 6897... |
+ // Second word is a BRA statement to ... anywhere
|
+ // Second word is a BRA statement to ... anywhere
|
+ // 0.1111.00010.ccc.0.iiiiiiiiiiiiiiiiii
|
+ // 0.1111.00010.ccc.0.iiiiiiiiiiiiiiiiii
|
+ // 0111.1000.10cc.c0ii.iiii.iiii.iiii.iiii
|
+ // 0111.1000.10cc.c0ii.iiii.iiii.iiii.iiii
|
+ if ((nxtword&0xffc40000) == 0x78800000)
|
+ if ((nxtword&0xffc40000) == 0x78800000)
|
+ return 1;
|
+ return 1;
|
|
+ // OR ... the second word could be a
|
|
+ // load into the PC
|
|
+ // 0.1111.10010.ccc.0.iiiiiiiiiiiiiiiiii LW.X #imm,PC
|
|
+ // 0.1111.10010.ccc.1.rrrr.iiiiiiiiiiiiii LW.X #(R),PC
|
|
+ //
|
|
+ // These must be unconditional, since the MOV above is
|
|
+ // also unconditional
|
|
+ // 0111.1100.10cc.cxxxxx.... LW.X #(R),PC
|
|
+ if ((nxtword&0xfff80000) == 0x7c800000)
|
|
+ return 1;
|
|
+ //
|
|
+ // OR ... the second word could be a
|
|
+ // Register move into the PC from the current
|
|
+ // register set
|
|
+ // 0.1111.01101.ccc.0.rrrr.0.iiiiiiiiiiiii MOV #(R),PC
|
|
+ // 0111.1011.01cc.c0rr.rr0i.iiiiiiiiiiii MOV #(R),PC
|
|
+ if ((nxtword&0xfffc2000) == 0x7b400000)
|
|
+ return 1;
|
|
+ //
|
+ return 0;
|
+ return 0;
|
+}
|
+}
|
+
|
+
|
+static inline int
|
+static inline int
|
+THREEWORD_LJSR(uint32_t iword, uint32_t nxtword) {
|
+THREEWORD_LJSR(uint32_t iword, uint32_t nxtword) {
|
Line 6849... |
Line 6931... |
+ return 1;
|
+ return 1;
|
+ return 0;
|
+ return 0;
|
+}
|
+}
|
+
|
+
|
+static inline int
|
+static inline int
|
+TWOWORD_CIS_JSR(uint32_t iword) {
|
+TWOWORD_CIS_LJSR(uint32_t iword) {
|
+ // MOV 2(PC) | LOD (PC),PC
|
+ // MOV 2(PC) | LOD (PC),PC
|
+ //
|
+ //
|
+ // 1.0000.111.1.1111.010
|
+ // 1.0000.111.1.1111.010
|
+ // 1.1111.100.1.1111.000
|
+ // 1.1111.100.1.1111.000
|
+ if (iword == 0x87fafcf8)
|
+ if (iword == 0x87fafcf8)
|
Line 6861... |
Line 6943... |
+ return 0;
|
+ return 0;
|
+}
|
+}
|
+
|
+
|
+static inline int
|
+static inline int
|
+CIS_JSR(uint32_t iword __attribute__((unused)) ) {
|
+CIS_JSR(uint32_t iword __attribute__((unused)) ) {
|
+ if (TWOWORD_CIS_JSR(iword))
|
+ if (TWOWORD_CIS_LJSR(iword))
|
+ return 1;
|
+ return 1;
|
+ // MOV 1(PC) | MOV Rx,PC
|
+ // MOV 1(PC) | MOV Rx,PC
|
+ //
|
+ //
|
+ // 1.0000.111.1.1111.001
|
+ // 1.0000.111.1.1111.001
|
+ // 1.1111.111.1.xxxx.000
|
+ // 1.1111.111.1.xxxx.000
|
Line 6883... |
Line 6965... |
+ if (iword == 0x0343c001)
|
+ if (iword == 0x0343c001)
|
+ return 1;
|
+ return 1;
|
+ // MOV 2(PC),PC
|
+ // MOV 2(PC),PC
|
+ if (iword == 0x0343c002)
|
+ if (iword == 0x0343c002)
|
+ return 1;
|
+ return 1;
|
+ if (TWOWORD_CIS_JSR(iword))
|
+ if (TWOWORD_CIS_LJSR(iword))
|
+ return 1;
|
+ return 1;
|
+ // The conditional LJMP is three words, which we don't handle ...
|
+ // The conditional LJMP is three words, which we don't handle ...
|
+ // Any BREV command could be the beginning of a twoword instruction
|
+ // Any BREV command could be the beginning of a twoword instruction
|
+ //
|
+ //
|
+ // Of course, the point here is to determine whether we should (or need
|
+ // Of course, the point here is to determine whether we should (or need
|
Line 6957... |
Line 7039... |
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+ sprintf(&line[strlen(line)], ",%s", zip_regstr[dv]);
|
+ sprintf(&line[strlen(line)], ",%s", zip_regstr[dv]);
|
+
|
+
|
+ return;
|
+ return;
|
+ } else if (TWOWORD_JSR(ins, nxtword)) {
|
+ } else if (TWOWORD_JSR(ins, nxtword)) {
|
|
+ if ((nxtword&0xffc40000) == 0x78800000) {
|
+ int cv = zip_getbits(nxtword, ZIP_BITFIELD(3,19));
|
+ int cv = zip_getbits(nxtword, ZIP_BITFIELD(3,19));
|
+ int iv = zip_sbits(nxtword, 18);
|
+ int iv = zip_sbits(nxtword, 18);
|
+
|
+
|
+ *refaddr = iv + addr + 8;
|
+ *refaddr = iv + addr + 8;
|
+ sprintf(line, "%s%s", "JSR", zip_ccstr[cv]);
|
+ sprintf(line, "%s%s", "JSR", zip_ccstr[cv]);
|
+ sprintf(line, "%-11s", line);
|
+ sprintf(line, "%-11s", line);
|
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+
|
+
|
+ return;
|
+ return;
|
+ } else if (TWOWORD_CIS_JSR(ins)) {
|
+ } else if ((nxtword&0xfff80000) == 0x7c800000) {
|
|
+ // OR ... the second word could be a load into the PC
|
|
+ if ((nxtword>>18)&1) {
|
|
+ // LW #(Rw),PC
|
|
+ int iv = zip_sbits(nxtword, 14);
|
|
+ int rb = zip_ubits(nxtword>>14, 4);
|
|
+
|
|
+ sprintf(line,"%-11s#%d(%s)", "IJSR", iv,
|
|
+ zip_regstr[rb]);
|
|
+ *refaddr = 0;
|
|
+ } else {
|
|
+ // LW (#),PC
|
|
+ int iv = zip_sbits(nxtword, 18);
|
|
+ sprintf(line,"%-11s(#%d)", "IJSR", iv);
|
|
+ *refaddr = iv;
|
|
+ }
|
|
+ return;
|
|
+ } else { // if ((nxtword&0xfffc2000) == 0x7b400000)
|
|
+ // OR ... the second word could be a register move into
|
|
+ // the PC from the current register set
|
|
+ int rb = zip_ubits(nxtword>>14, 4);
|
|
+ int iv = zip_sbits(nxtword, 13);
|
|
+
|
|
+ *refaddr = 0;
|
|
+ if (iv == 0)
|
|
+ sprintf(line, "%-11s %s", "JSR",
|
|
+ zip_regstr[rb]);
|
|
+ else
|
|
+ sprintf(line, "%-11s#%d+%s", "JSR",iv,
|
|
+ zip_regstr[rb]);
|
|
+
|
|
+ return;
|
|
+ }
|
|
+ } else if (TWOWORD_CIS_LJSR(ins)) {
|
+ *refaddr = nxtword;
|
+ *refaddr = nxtword;
|
+ sprintf(line, "%-11s", "JSR");
|
+ sprintf(line, "%-11s", "LJSR");
|
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+ sprintf(line, "%s0x%08x", line, *refaddr);
|
+ return;
|
+ return;
|
+ } else if (CIS_JSR(ins)) {
|
+ } else if (CIS_JSR(ins)) {
|
+ int ra = zip_getbits(ins, ZIP_REGFIELD(3));
|
+ int ra = zip_getbits(ins, ZIP_REGFIELD(3));
|
+ sprintf(line, "%-11s%s", "JSR", zip_regstr[ra]);
|
+ sprintf(line, "%-11s%s", "JSR", zip_regstr[ra]);
|
Line 7166... |
Line 7282... |
+ if (THREEWORD_LJSR(iword,nxtword)) {
|
+ if (THREEWORD_LJSR(iword,nxtword)) {
|
+ sprintf(astr, "%-11s", "LJSR");
|
+ sprintf(astr, "%-11s", "LJSR");
|
+ if ((*info->read_memory_func)(vma, ibytes, 12, info) ==0)
|
+ if ((*info->read_memory_func)(vma, ibytes, 12, info) ==0)
|
+ refaddr = (ibytes[8]<<24)|(ibytes[9]<<16)|(ibytes[10]<<8)|(ibytes[11]);
|
+ refaddr = (ibytes[8]<<24)|(ibytes[9]<<16)|(ibytes[10]<<8)|(ibytes[11]);
|
+ sprintf(&astr[strlen(astr)], "@0x%08x", refaddr);
|
+ sprintf(&astr[strlen(astr)], "@0x%08x", refaddr);
|
+ } else if (TWOWORD_CIS_JSR(iword)) {
|
+ } else if (TWOWORD_CIS_LJSR(iword)) {
|
+ refaddr = nxtword;
|
+ refaddr = nxtword;
|
+ sprintf(astr, "%-11s0x%08x", "JSR", refaddr);
|
+ sprintf(astr, "%-11s0x%08x", "JSR", refaddr);
|
+ } else
|
+ } else
|
+ zipi_to_double_string(vma, iword, nxtword, astr, bstr,&refaddr);
|
+ zipi_to_double_string(vma, iword, nxtword, astr, bstr,&refaddr);
|
+
|
+
|
Line 7207... |
Line 7323... |
+ // must match as well.
|
+ // must match as well.
|
+ if (TWOWORD_LOAD(iword,nxtword))
|
+ if (TWOWORD_LOAD(iword,nxtword))
|
+ return 8;
|
+ return 8;
|
+ if (TWOWORD_JSR(iword,nxtword))
|
+ if (TWOWORD_JSR(iword,nxtword))
|
+ return 8;
|
+ return 8;
|
+ if (TWOWORD_CIS_JSR(iword))
|
+ if (TWOWORD_CIS_LJSR(iword))
|
+ return 8;
|
+ return 8;
|
+ return 4;
|
+ return 4;
|
+}
|
+}
|
+
|
+
|
+
|
+
|
Line 7219... |
Line 7335... |
+zip_get_disassembler(bfd *abfd ATTRIBUTE_UNUSED)
|
+zip_get_disassembler(bfd *abfd ATTRIBUTE_UNUSED)
|
+{
|
+{
|
+ return print_zip_insn;
|
+ return print_zip_insn;
|
+}
|
+}
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.h binutils-2.27-zip/opcodes/zip-dis.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-dis.h binutils-2.27-zip/opcodes/zip-dis.h
|
--- binutils-2.27/opcodes/zip-dis.h 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/opcodes/zip-dis.h 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/zip-dis.h 2016-12-31 18:10:03.512012534 -0500
|
+++ binutils-2.27-zip/opcodes/zip-dis.h 2016-12-31 18:10:03.512012534 -0500
|
@@ -0,0 +1,45 @@
|
@@ -0,0 +1,45 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-dis.h
|
+// Filename: zip-dis.h
|
Line 7268... |
Line 7384... |
+
|
+
|
+extern disassembler_ftype
|
+extern disassembler_ftype
|
+zip_get_disassembler(bfd *abfd);
|
+zip_get_disassembler(bfd *abfd);
|
+
|
+
|
+#endif
|
+#endif
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.c binutils-2.27-zip/opcodes/zip-opc.c
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-opc.c binutils-2.27-zip/opcodes/zip-opc.c
|
--- binutils-2.27/opcodes/zip-opc.c 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/opcodes/zip-opc.c 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/zip-opc.c 2017-03-06 14:00:55.404955681 -0500
|
+++ binutils-2.27-zip/opcodes/zip-opc.c 2018-06-07 10:35:06.439245343 -0400
|
@@ -0,0 +1,362 @@
|
@@ -0,0 +1,362 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-opc.c
|
+// Filename: zip-opc.c
|
+//
|
+//
|
Line 7549... |
Line 7665... |
+ // 1.rrrr.010.1.rrrrsss
|
+ // 1.rrrr.010.1.rrrrsss
|
+ { "ADD", 0x87800000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
+ { "ADD", 0x87800000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
+ { "ADD", 0x87800000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
|
+ { "ADD", 0x87800000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
|
+ //
|
+ //
|
+ // 1.rrrr.011.a.rrrrsss
|
+ // 1.rrrr.011.a.rrrrsss
|
+ { "CMP", 0x87800000, 0x83000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
+ { "CMP", 0x87800000, 0x83000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
+ { "CMP", 0x87800000, 0x83800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
|
+ { "CMP", 0x87800000, 0x83800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
|
+ //
|
+ //
|
+ // 1.rrrr.100.0.sssssss
|
+ // 1.rrrr.100.0.sssssss
|
+ // 1.rrrr.100.1.rrrrsss
|
+ // 1.rrrr.100.1.rrrrsss
|
+ { "LW", 0x87800000, 0x84000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
+ { "LW", 0x87800000, 0x84000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
|
Line 7634... |
Line 7750... |
+ *zip_opbottomlist = zip_opbottomlist_raw;
|
+ *zip_opbottomlist = zip_opbottomlist_raw;
|
+
|
+
|
+const int nzip_oplist = (sizeof(zip_oplist_raw)/sizeof(ZOPCODE));
|
+const int nzip_oplist = (sizeof(zip_oplist_raw)/sizeof(ZOPCODE));
|
+const int nzip_opbottom = (sizeof(zip_opbottomlist_raw)/sizeof(ZOPCODE));
|
+const int nzip_opbottom = (sizeof(zip_opbottomlist_raw)/sizeof(ZOPCODE));
|
+
|
+
|
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.h binutils-2.27-zip/opcodes/zip-opc.h
|
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-opc.h binutils-2.27-zip/opcodes/zip-opc.h
|
--- binutils-2.27/opcodes/zip-opc.h 1969-12-31 19:00:00.000000000 -0500
|
--- binutils-2.27-original/opcodes/zip-opc.h 1969-12-31 19:00:00.000000000 -0500
|
+++ binutils-2.27-zip/opcodes/zip-opc.h 2017-02-10 17:48:01.761470841 -0500
|
+++ binutils-2.27-zip/opcodes/zip-opc.h 2017-02-10 17:48:01.761470841 -0500
|
@@ -0,0 +1,77 @@
|
@@ -0,0 +1,77 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-opc.h
|
+// Filename: zip-opc.h
|