| Line 136... |
Line 136... |
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
+
|
+
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
|
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-04-21 20:04:11.745606740 -0400
|
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400
|
@@ -21,7 +21,7 @@
|
@@ -21,7 +21,7 @@
|
#ifndef GCC_AARCH64_LINUX_H
|
#ifndef GCC_AARCH64_LINUX_H
|
#define GCC_AARCH64_LINUX_H
|
#define GCC_AARCH64_LINUX_H
|
|
|
| Line 148... |
Line 148... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
|
|
#undef ASAN_CC1_SPEC
|
#undef ASAN_CC1_SPEC
|
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
|
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
|
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -23,8 +23,8 @@
|
@@ -23,8 +23,8 @@
|
#define EXTRA_SPECS \
|
#define EXTRA_SPECS \
|
{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
|
{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
|
|
|
| Line 162... |
Line 162... |
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
|
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -68,8 +68,8 @@
|
@@ -68,8 +68,8 @@
|
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */
|
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */
|
|
|
#undef GLIBC_DYNAMIC_LINKER
|
#undef GLIBC_DYNAMIC_LINKER
|
| Line 176... |
Line 176... |
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
|
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
|
#define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
|
#define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
|
|
|
#define GLIBC_DYNAMIC_LINKER \
|
#define GLIBC_DYNAMIC_LINKER \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
|
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400
|
@@ -62,7 +62,7 @@
|
@@ -62,7 +62,7 @@
|
|
|
#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
|
#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
|
|
|
| Line 188... |
Line 188... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
#define LINUX_TARGET_LINK_SPEC "%{h*} \
|
#define LINUX_TARGET_LINK_SPEC "%{h*} \
|
%{static:-Bstatic} \
|
%{static:-Bstatic} \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
|
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -45,7 +45,7 @@
|
@@ -45,7 +45,7 @@
|
%{shared:-G -Bdynamic} \
|
%{shared:-G -Bdynamic} \
|
%{!shared: %{!static: \
|
%{!shared: %{!static: \
|
%{rdynamic:-export-dynamic} \
|
%{rdynamic:-export-dynamic} \
|
| Line 200... |
Line 200... |
+ -dynamic-linker /lib/ld-uClibc.so.0} \
|
+ -dynamic-linker /lib/ld-uClibc.so.0} \
|
%{static}} -init __init -fini __fini"
|
%{static}} -init __init -fini __fini"
|
|
|
#undef TARGET_SUPPORTS_SYNC_CALLS
|
#undef TARGET_SUPPORTS_SYNC_CALLS
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
|
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -102,7 +102,7 @@
|
@@ -102,7 +102,7 @@
|
#undef CRIS_DEFAULT_CPU_VERSION
|
#undef CRIS_DEFAULT_CPU_VERSION
|
#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
|
#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
|
|
|
| Line 212... |
Line 212... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
#undef CRIS_LINK_SUBTARGET_SPEC
|
#undef CRIS_LINK_SUBTARGET_SPEC
|
#define CRIS_LINK_SUBTARGET_SPEC \
|
#define CRIS_LINK_SUBTARGET_SPEC \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
|
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-13 12:14:18.252711082 -0400
|
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400
|
@@ -129,9 +129,9 @@
|
@@ -129,9 +129,9 @@
|
#endif
|
#endif
|
|
|
#if FBSD_MAJOR < 6
|
#if FBSD_MAJOR < 6
|
| Line 227... |
Line 227... |
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
|
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
|
#endif
|
#endif
|
|
|
/* NOTE: The freebsd-spec.h header is included also for various
|
/* NOTE: The freebsd-spec.h header is included also for various
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
|
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -34,7 +34,7 @@
|
@@ -34,7 +34,7 @@
|
#define ENDFILE_SPEC \
|
#define ENDFILE_SPEC \
|
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
|
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
|
|
|
| Line 239... |
Line 239... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "\
|
#define LINK_SPEC "\
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
|
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -22,7 +22,7 @@
|
@@ -22,7 +22,7 @@
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
#undef GNU_USER_DYNAMIC_LINKER
|
| Line 251... |
Line 251... |
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
|
|
|
#undef STARTFILE_SPEC
|
#undef STARTFILE_SPEC
|
#if defined HAVE_LD_PIE
|
#if defined HAVE_LD_PIE
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -22,6 +22,6 @@
|
@@ -22,6 +22,6 @@
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
|
|
|
| Line 264... |
Line 264... |
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
|
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
|
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -19,4 +19,4 @@
|
@@ -19,4 +19,4 @@
|
<http://www.gnu.org/licenses/>. */
|
<http://www.gnu.org/licenses/>. */
|
|
|
#define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
|
#define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
|
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -27,6 +27,6 @@
|
@@ -27,6 +27,6 @@
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64"
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64"
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
|
|
|
| Line 286... |
Line 286... |
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
|
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
|
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
|
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -20,4 +20,4 @@
|
@@ -20,4 +20,4 @@
|
<http://www.gnu.org/licenses/>. */
|
<http://www.gnu.org/licenses/>. */
|
|
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
|
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -55,7 +55,7 @@
|
@@ -55,7 +55,7 @@
|
/* Define this for shared library support because it isn't in the main
|
/* Define this for shared library support because it isn't in the main
|
linux.h file. */
|
linux.h file. */
|
|
|
| Line 307... |
Line 307... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "\
|
#define LINK_SPEC "\
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
|
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -32,4 +32,4 @@
|
@@ -32,4 +32,4 @@
|
|
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
#undef GNU_USER_DYNAMIC_LINKER
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
|
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -31,5 +31,4 @@
|
@@ -31,5 +31,4 @@
|
while (0)
|
while (0)
|
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
#undef GNU_USER_DYNAMIC_LINKER
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
-
|
-
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
|
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -73,10 +73,10 @@
|
@@ -73,10 +73,10 @@
|
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
|
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
|
GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
|
GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
|
supporting both 32-bit and 64-bit compilation. */
|
supporting both 32-bit and 64-bit compilation. */
|
| Line 344... |
Line 344... |
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
|
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
|
#define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
|
#define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
|
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
|
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
|
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
|
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
|
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -67,7 +67,7 @@
|
@@ -67,7 +67,7 @@
|
%{shared:-shared} \
|
%{shared:-shared} \
|
%{symbolic:-Bsymbolic} \
|
%{symbolic:-Bsymbolic} \
|
%{rdynamic:-export-dynamic} \
|
%{rdynamic:-export-dynamic} \
|
| Line 356... |
Line 356... |
+ -dynamic-linker /lib/ld-linux.so.2"
|
+ -dynamic-linker /lib/ld-linux.so.2"
|
|
|
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
|
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
|
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -71,7 +71,7 @@
|
@@ -71,7 +71,7 @@
|
When the -shared link option is used a final link is not being
|
When the -shared link option is used a final link is not being
|
done. */
|
done. */
|
|
|
| Line 368... |
Line 368... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "-m m68kelf %{shared} \
|
#define LINK_SPEC "-m m68kelf %{shared} \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
|
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
|
@@ -28,7 +28,7 @@
|
@@ -28,7 +28,7 @@
|
#undef TLS_NEEDS_GOT
|
#undef TLS_NEEDS_GOT
|
#define TLS_NEEDS_GOT 1
|
#define TLS_NEEDS_GOT 1
|
|
|
| Line 380... |
Line 380... |
+#define DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define DYNAMIC_LINKER "/lib/ld.so.1"
|
#undef SUBTARGET_EXTRA_SPECS
|
#undef SUBTARGET_EXTRA_SPECS
|
#define SUBTARGET_EXTRA_SPECS \
|
#define SUBTARGET_EXTRA_SPECS \
|
{ "dynamic_linker", DYNAMIC_LINKER }
|
{ "dynamic_linker", DYNAMIC_LINKER }
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
|
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -22,20 +22,20 @@
|
@@ -22,20 +22,20 @@
|
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
|
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
|
|
|
#define GLIBC_DYNAMIC_LINKER32 \
|
#define GLIBC_DYNAMIC_LINKER32 \
|
| Line 410... |
Line 410... |
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
|
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
|
|
|
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
|
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
|
#define GNU_USER_DYNAMIC_LINKERN32 \
|
#define GNU_USER_DYNAMIC_LINKERN32 \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
|
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -32,7 +32,7 @@
|
@@ -32,7 +32,7 @@
|
#undef ASM_SPEC
|
#undef ASM_SPEC
|
#define ASM_SPEC ""
|
#define ASM_SPEC ""
|
|
|
| Line 422... |
Line 422... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
|
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
|
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400
|
@@ -37,7 +37,7 @@
|
@@ -37,7 +37,7 @@
|
/* Define this for shared library support because it isn't in the main
|
/* Define this for shared library support because it isn't in the main
|
linux.h file. */
|
linux.h file. */
|
|
|
| Line 434... |
Line 434... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "\
|
#define LINK_SPEC "\
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
|
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400
|
@@ -357,14 +357,14 @@
|
@@ -357,14 +357,14 @@
|
#undef LINK_OS_DEFAULT_SPEC
|
#undef LINK_OS_DEFAULT_SPEC
|
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
|
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
|
|
|
| Line 457... |
Line 457... |
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
|
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400
|
@@ -757,8 +757,8 @@
|
@@ -757,8 +757,8 @@
|
|
|
#define LINK_START_LINUX_SPEC ""
|
#define LINK_START_LINUX_SPEC ""
|
|
|
| Line 471... |
Line 471... |
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
|
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
|
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400
|
@@ -60,8 +60,8 @@
|
@@ -60,8 +60,8 @@
|
#define MULTILIB_DEFAULTS { "m31" }
|
#define MULTILIB_DEFAULTS { "m31" }
|
#endif
|
#endif
|
|
|
| Line 485... |
Line 485... |
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC \
|
#define LINK_SPEC \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
|
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -43,7 +43,7 @@
|
@@ -43,7 +43,7 @@
|
|
|
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
|
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
|
|
|
| Line 497... |
Line 497... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
#undef SUBTARGET_LINK_EMUL_SUFFIX
|
#undef SUBTARGET_LINK_EMUL_SUFFIX
|
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
|
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
|
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -84,8 +84,8 @@
|
@@ -84,8 +84,8 @@
|
When the -shared link option is used a final link is not being
|
When the -shared link option is used a final link is not being
|
done. */
|
done. */
|
|
|
| Line 520... |
Line 520... |
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
|
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
|
%{!shared: \
|
%{!shared: \
|
%{!static: \
|
%{!static: \
|
%{rdynamic:-export-dynamic} \
|
%{rdynamic:-export-dynamic} \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
|
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -83,7 +83,7 @@
|
@@ -83,7 +83,7 @@
|
When the -shared link option is used a final link is not being
|
When the -shared link option is used a final link is not being
|
done. */
|
done. */
|
|
|
| Line 532... |
Line 532... |
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
|
|
#undef LINK_SPEC
|
#undef LINK_SPEC
|
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
|
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
|
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -41,7 +41,7 @@
|
@@ -41,7 +41,7 @@
|
%{!shared: \
|
%{!shared: \
|
%{!static: \
|
%{!static: \
|
%{rdynamic:-export-dynamic} \
|
%{rdynamic:-export-dynamic} \
|
| Line 544... |
Line 544... |
+ -dynamic-linker /lib/ld.so.1} \
|
+ -dynamic-linker /lib/ld.so.1} \
|
%{static:-static}}"
|
%{static:-static}}"
|
|
|
#undef WCHAR_TYPE
|
#undef WCHAR_TYPE
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
|
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-13 12:14:18.256711056 -0400
|
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-04-21 20:04:11.761606648 -0400
|
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500
|
@@ -44,7 +44,7 @@
|
@@ -44,7 +44,7 @@
|
%{mlongcalls:--longcalls} \
|
%{mlongcalls:--longcalls} \
|
%{mno-longcalls:--no-longcalls}"
|
%{mno-longcalls:--no-longcalls}"
|
|
|
| Line 694... |
Line 694... |
+ # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
+ # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
+
|
+
|
+
|
+
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
|
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-07 16:23:35.651592937 -0400
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-04-21 16:52:37.544818916 -0400
|
@@ -0,0 +1,2126 @@
|
@@ -0,0 +1,2174 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip.c
|
+// Filename: zip.c
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
| Line 931... |
Line 931... |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) zip_debug_rtx(x);
|
+ if (dbg) zip_debug_rtx(x);
|
+ switch(GET_CODE(x)) {
|
+ switch(GET_CODE(x)) {
|
+ case REG:
|
+ case REG:
|
|
+ gcc_assert(is_ZIP_REG(REGNO(x)));
|
+ fprintf(file, "(%s)", reg_names[REGNO(x)]);
|
+ fprintf(file, "(%s)", reg_names[REGNO(x)]);
|
+ break;
|
+ break;
|
+ case SYMBOL_REF:
|
+ case SYMBOL_REF:
|
+ fprintf(file, "%s", XSTR(x,0));
|
+ fprintf(file, "%s", XSTR(x,0));
|
+ break;
|
+ break;
|
| Line 953... |
Line 954... |
+ case PLUS:
|
+ case PLUS:
|
+ if (!REG_P(XEXP(x, 0))) {
|
+ if (!REG_P(XEXP(x, 0))) {
|
+ fprintf(stderr, "Unsupported address construct\n");
|
+ fprintf(stderr, "Unsupported address construct\n");
|
+ zip_debug_rtx(x);
|
+ zip_debug_rtx(x);
|
+ abort();
|
+ abort();
|
+ } if (CONST_INT_P(XEXP(x, 1))) {
|
+ } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
|
|
+ if (CONST_INT_P(XEXP(x, 1))) {
|
+ if (INTVAL(XEXP(x,1))!=0) {
|
+ if (INTVAL(XEXP(x,1))!=0) {
|
+ fprintf(file, "%ld(%s)",
|
+ fprintf(file, "%ld(%s)",
|
+ INTVAL(XEXP(x, 1)),
|
+ INTVAL(XEXP(x, 1)),
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
+ } else {
|
+ } else {
|
| Line 1196... |
Line 1198... |
+
|
+
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ zip_compute_frame();
|
+ zip_compute_frame();
|
+
|
+
|
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
|
|
+ cfun->machine->sp_fp_offset);
|
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx,
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
+ SImode)));
|
+ SImode)));
|
| Line 1210... |
Line 1214... |
+
|
+
|
+ {
|
+ {
|
+ int offset = 0, regno;
|
+ int offset = 0, regno;
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
+ if (zip_save_reg(regno)) {
|
+ if (zip_save_reg(regno)) {
|
|
+ if (dbg) fprintf(stderr,
|
|
+ "PROLOGUE: Saving R%d in %d+%d(SP)\n",
|
|
+ regno, cfun->machine->sp_fp_offset,
|
|
+ offset);
|
+ insn=emit_insn(gen_movsi_sto_off(
|
+ insn=emit_insn(gen_movsi_sto_off(
|
+ stack_pointer_rtx,
|
+ stack_pointer_rtx,
|
+ GEN_INT(cfun->machine->sp_fp_offset
|
+ GEN_INT(cfun->machine->sp_fp_offset
|
+ +offset++),
|
+ +offset++),
|
+ gen_rtx_REG(SImode, regno)));
|
+ gen_rtx_REG(SImode, regno)));
|
| Line 2018... |
Line 2026... |
+ zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
|
+ zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ debug_rtx(x);
|
+ debug_rtx(x);
|
+ break;
|
+ break;
|
+ case REG: {
|
+ case REG: {
|
+ char buf[25];
|
+ char buf[25], mstr[4];
|
|
+ mstr[0] = '\0';
|
|
+ if (GET_MODE(x) == SImode)
|
|
+ strcpy(mstr, ":SI");
|
|
+ else if (GET_MODE(x) == DImode)
|
|
+ strcpy(mstr, ":DI");
|
|
+ else if (GET_MODE(x) == VOIDmode)
|
|
+ strcpy(mstr, ":V");
|
+ if (REGNO(x) == zip_PC)
|
+ if (REGNO(x) == zip_PC)
|
+ sprintf(buf, "(PC)");
|
+ sprintf(buf, "(PC%s)", mstr);
|
+ else if (REGNO(x) == zip_CC)
|
+ else if (REGNO(x) == zip_CC)
|
+ sprintf(buf, "(CC)");
|
+ sprintf(buf, "(CC%s)", mstr);
|
+ else if (REGNO(x) == zip_SP)
|
+ else if (REGNO(x) == zip_SP)
|
+ sprintf(buf, "(SP)");
|
+ sprintf(buf, "(SP%s)", mstr);
|
+ else if (REGNO(x) == zip_FP)
|
+ else if (REGNO(x) == zip_FP)
|
+ sprintf(buf, "(REG FP)");
|
+ sprintf(buf, "(REG%s FP)", mstr);
|
+ else if (REGNO(x) == zip_GOT)
|
+ else if (REGNO(x) == zip_GOT)
|
+ sprintf(buf, "(REG GBL)");
|
+ sprintf(buf, "(REG%s GBL)", mstr);
|
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
|
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
|
+ sprintf(buf, "(REG RTN-VL)");
|
+ sprintf(buf, "(REG%s RTN-VL)", mstr);
|
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
|
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
|
+ sprintf(buf, "(REG RTN-AD)");
|
+ sprintf(buf, "(REG%s RTN-AD)", mstr);
|
|
+ else
|
|
+ sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
|
|
+ if (mstr[0])
|
|
+ zip_debug_print(pfx, lvl, buf);
|
+ else
|
+ else
|
+ sprintf(buf, "(REG %d)", REGNO(x));
|
|
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
+ } break;
|
+ } break;
|
+ case IF_THEN_ELSE: // 51
|
+ case IF_THEN_ELSE: // 51
|
+ zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
|
+ zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
| Line 2051... |
Line 2069... |
+ break;
|
+ break;
|
+ case CC0:
|
+ case CC0:
|
+ zip_debug_print(pfx, lvl, "(CC0)");
|
+ zip_debug_print(pfx, lvl, "(CC0)");
|
+ break;
|
+ break;
|
+ case COMPARE:
|
+ case COMPARE:
|
+ zip_debug_print(pfx, lvl, "(COMPARE");
|
+ zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ break;
|
+ break;
|
+ case CONST:
|
+ case CONST:
|
| Line 2216... |
Line 2234... |
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
+ zip_debug_print(pfx, lvl, ")");
|
+ zip_debug_print(pfx, lvl, ")");
|
+ }}
|
+ }}
|
+ break;
|
+ break;
|
|
+ case ASHIFT:
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
|
+ zip_debug_print(pfx, lvl, ")");
|
|
+ break;
|
|
+ case ASHIFTRT:
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
|
+ zip_debug_print(pfx, lvl, ")");
|
|
+ break;
|
|
+ case LSHIFTRT:
|
|
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
|
+ zip_debug_print(pfx, lvl, ")");
|
|
+ break;
|
+ default:
|
+ default:
|
+ { char buf[128];
|
+ { char buf[128];
|
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
+ zip_debug_print(pfx, lvl, buf);
|
+ zip_debug_print(pfx, lvl, buf);
|
+ debug_rtx(x);
|
+ debug_rtx(x);
|
| Line 2412... |
Line 2448... |
+zip_const_address_operand(rtx x) {
|
+zip_const_address_operand(rtx x) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+
|
+
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
+ if (dbg) zip_debug_rtx(x);
|
+ if (dbg) zip_debug_rtx(x);
|
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode))
|
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
|
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
|
+ return false;
|
+ return false;
|
|
+ }
|
+ if ((GET_CODE(x) == LABEL_REF)
|
+ if ((GET_CODE(x) == LABEL_REF)
|
+ ||(GET_CODE(x) == CODE_LABEL)
|
+ ||(GET_CODE(x) == CODE_LABEL)
|
+ ||(GET_CODE(x) == SYMBOL_REF)) {
|
+ ||(GET_CODE(x) == SYMBOL_REF)) {
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES!\n");
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
|
+ return true;
|
+ return true;
|
+ } else if (CONST_INT_P(x)) {
|
+ } else if (CONST_INT_P(x)) {
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES!\n");
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
|
+ return true;
|
+ return true;
|
+ } else if (GET_CODE(x) == PLUS) {
|
+ } else if (GET_CODE(x) == PLUS) {
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
+ &&(CONST_INT_P(XEXP(x,1))));
|
+ &&(CONST_INT_P(XEXP(x,1))));
|
| Line 2533... |
Line 2571... |
+ internal_error("CSTORE Unsupported condition");
|
+ internal_error("CSTORE Unsupported condition");
|
+ return NULL;
|
+ return NULL;
|
+ }
|
+ }
|
+}
|
+}
|
+
|
+
|
|
+/*
|
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
|
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
|
+ static char result[64] = "";
|
+ static char result[64] = "";
|
+ switch(condition) {
|
+ switch(condition) {
|
+ //
|
+ //
|
+ // Result already exists in the iffalse register
|
+ // Result already exists in the iffalse register
|
| Line 2579... |
Line 2618... |
+ default:
|
+ default:
|
+ internal_error("MOVSICC(BINARY) Unsupported condition");
|
+ internal_error("MOVSICC(BINARY) Unsupported condition");
|
+ return NULL;
|
+ return NULL;
|
+ } return result;
|
+ } return result;
|
+}
|
+}
|
|
+*/
|
+
|
+
|
+const char *zip_tertiary_movsicc(rtx condition, const char *optrue, const char *opfalse) {
|
+bool
|
+ static char result[64] = "";
|
+zip_supported_condition(int c) {
|
+ switch(GET_CODE(condition)) {
|
+ switch(c) {
|
+ case EQ: sprintf(result,"%s\t%%3,%%0\n\t%s.Z\t%%2,%%0", opfalse, optrue); break;
|
+ case NE: case LT: case EQ: case GT: case GE: case LTU:
|
+ case NE: sprintf(result,"%s\t%%3,%%0\n\t%s.NZ\t%%2,%%0", opfalse, optrue); break;
|
+ return true;
|
+ case LT: sprintf(result,"%s\t%%3,%%0\n\t%s.LT\t%%2,%%0", opfalse, optrue); break;
|
+ break;
|
+ case GT: sprintf(result,"%s\t%%3,%%0\n\t%s.GT\t%%2,%%0", opfalse, optrue); break;
|
|
+ // LE doesn't exist on a Zip CPU. Accomplish this by
|
|
+ // reversing the condition: i.e., load the false value into
|
|
+ // the register, and the on condition load the true value.
|
|
+ case LE: sprintf(result,"%s\t%%2,%%0\n\t%s.GT\t%%3,%%0", optrue, opfalse); break;
|
|
+ case GE: sprintf(result,"%s\t%%3,%%0\n\t%s.GE\t%%2,%%0", opfalse, optrue); break;
|
|
+ case LTU: sprintf(result,"%s\t%%3,%%0\n\t%s.C\t%%2,%%0", opfalse, optrue); break;
|
|
+ //
|
|
+ case GTU: sprintf(result,"%s\t%%2,%%0\n\t%s.C\t%%3,%%0\n\t%s.Z\t%%3,%%0", optrue, opfalse, opfalse); break;
|
|
+ case LEU: sprintf(result,"%s\t%%3,%%0\n\t%s.C\t%%2,%%0\n\t%s.Z\t%%2,%%0", opfalse, optrue, optrue); break;
|
|
+ case GEU: sprintf(result,"%s\t%%2,%%0\n\t%s.C\t%%3,%%0\n", optrue, opfalse); break;
|
|
+ default:
|
+ default:
|
+ internal_error("MOVSICC Unsupported condition");
|
+ break;
|
+ return NULL;
|
+ } return false;
|
+ } return result;
|
+}
|
|
+
|
|
+bool
|
|
+zip_signed_comparison(int c) {
|
|
+ switch(c) {
|
|
+ case NE: case LT: case EQ: case GT: case GE:
|
|
+ return true;
|
|
+ default:
|
|
+ break;
|
|
+ } return false;
|
+}
|
+}
|
+
|
+
|
+const char *zip_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
|
+void
|
|
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
|
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
+ if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
|
+ if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
|
+ if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
|
+ if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
|
+ if ((REG_P(iftrue))&&(REGNO(dst)==REGNO(iftrue))) {
|
+
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- CASE if(X) -> R\n");
|
+ // Start with the condition
|
+ if (zip_legitimate_move_operand_p(SImode, iffalse, true))
|
+ rtx cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
|
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "MOV", 3);
|
+ enum rtx_code cmpcode = GET_CODE(condition);
|
+ else if (zip_const_address_operand(iffalse))
|
+
|
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
|
+ //; Do we need to swap or adjust the condition?
|
+ else if (zip_const_address_operand(iffalse))
|
+ if (zip_supported_condition((int)cmpcode)) {
|
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
|
+ // Keep everything as is
|
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
|
+ } else if ((zip_supported_condition(reverse_condition(cmpcode)))
|
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LOD", 3);
|
+ &&(!MEM_P(iffalse))) {
|
+ else {
|
+ rtx tem = iffalse;
|
+ internal_error("MOVSICC Unsupported mode");
|
+ iffalse = iftrue;
|
+ return NULL;
|
+ iftrue = tem;
|
+ }
|
+
|
+ } if ((REG_P(iftrue))&&(REGNO(dst)==REGNO(iftrue))) {
|
+ cmpcode = reverse_condition(cmpcode);
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- CASE if(!X) -> R\n");
|
+ } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
|
+ if (zip_legitimate_move_operand_p(SImode, iftrue, true))
|
+ &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
|
+ return zip_binary_movsicc(GET_CODE(condition), "MOV",2);
|
+ rtx tem = cmpa;
|
+ else if (zip_const_address_operand(iffalse))
|
+ cmpa = cmpb;
|
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
|
+ cmpa = tem;
|
+ else if (zip_const_address_operand(iffalse))
|
+ cmpcode = swap_condition(cmpcode);
|
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
|
+
|
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
|
+ if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
|
+ return zip_binary_movsicc(GET_CODE(condition), "LOD",2);
|
+ &&(REG_P(XEXP(cmpa,0)))
|
+ else {
|
+ &&(CONST_INT_P(XEXP(cmpa,1)))
|
+ internal_error("MOVSICC Unsupported mode");
|
+ &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
|
+ return NULL;
|
+
|
|
+ // If we were doing CMP x(Rb),Ra
|
|
+ // and we just changed it to CMP Ra,x(Rb)
|
|
+ // adjust it to CMP -x(Ra),Rb
|
|
+ cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
|
|
+ cmpa = XEXP(cmpa,0);
|
|
+ } else if (!REG_P(cmpa)) {
|
|
+ // Otherwise, if we had anything else in Rb other than
|
|
+ // a register ... such as a constant, then load it into
|
|
+ // a register before comparing it. So
|
|
+ // CMP x,Ra
|
|
+ // became
|
|
+ // CMP Ra,x
|
|
+ // now becomes
|
|
+ // LDI x,Rt
|
|
+ // CMP Ra,Rt
|
|
+ // (We already tested for can_create_pseudo_p() above..)
|
|
+ tem = gen_reg_rtx(SImode);
|
|
+ emit_move_insn(tem, cmpa);
|
|
+ cmpa = tem;
|
+ }
|
+ }
|
+ } if ((zip_const_address_operand(iftrue))&&(zip_const_address_operand(iffalse))) {
|
+ } else {
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #1 ELSE #2\n");
|
+ // Here's our last chance.
|
+ return zip_tertiary_movsicc(condition, "LDI", "LDI");
|
+ // This will adjust for less than equal types of stuff
|
+ } if ((zip_const_address_operand(iftrue))&&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
|
+ int cod = (int)cmpcode;
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #1 ELSE A+B\n");
|
+ zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
|
+ return zip_tertiary_movsicc(condition, "LDI", "MOV");
|
+ cmpcode = (enum rtx_code)cod;
|
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))&&(zip_const_address_operand(iffalse))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE #x\n");
|
|
+ return zip_tertiary_movsicc(condition, "MOV", "LDI");
|
|
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))
|
|
+ &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C+D\n");
|
|
+ return zip_tertiary_movsicc(condition, "MOV", "MOV");
|
|
+ }
|
|
+ if ((MEM_P(iftrue))
|
|
+ &&(zip_legitimate_opb(XEXP(iftrue,0), true))
|
|
+ &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C+D\n");
|
|
+ return zip_tertiary_movsicc(condition, "LOD", "MOV");
|
|
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))
|
|
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C[D]\n");
|
|
+ return zip_tertiary_movsicc(condition, "MOV", "LOD");
|
|
+ } if ((MEM_P(iftrue))&&(zip_legitimate_opb(XEXP(iftrue,0), true))
|
|
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C[D]\n");
|
|
+ return zip_tertiary_movsicc(condition, "LOD", "LOD");
|
|
+ } if ((MEM_P(iftrue))
|
|
+ &&(zip_legitimate_opb(XEXP(iftrue,0),true))
|
|
+ &&(zip_const_address_operand(iffalse))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE #x\n");
|
|
+ return zip_tertiary_movsicc(condition, "LOD", "LDI");
|
|
+ } if ((MEM_P(iffalse))
|
|
+ &&(zip_legitimate_opb(XEXP(iffalse,0),true))
|
|
+ &&(zip_const_address_operand(iftrue))) {
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #x ELSE A[B]\n");
|
|
+ return zip_tertiary_movsicc(condition, "LDI", "LOD");
|
|
+ }
|
+ }
|
+
|
+
|
+ internal_error("MOVSICC Operands not supported");
|
+ gcc_assert(zip_supported_condition((int)cmpcode));
|
|
+
|
|
+ //; Always do the default move
|
|
+ emit_move_insn(dst, iffalse);
|
|
+
|
|
+ rtx cc_rtx = gen_rtx_REG(CCmode, zip_CC);
|
|
+
|
|
+ //; Now let's get our comparison right
|
|
+ emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
|
|
+ gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
|
|
+
|
|
+ //; Finally, let's load the value on true
|
|
+ emit_insn(gen_movsicc_bare(dst,
|
|
+ gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
|
|
+ iftrue, dst));
|
+}
|
+}
|
+
|
+
|
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
|
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
|
+ // We know upon entry that REG_P(dst) must be true
|
+ // We know upon entry that REG_P(dst) must be true
|
+ if (!REG_P(dst))
|
+ if (!REG_P(dst))
|
| Line 2822... |
Line 2863... |
+ if (ifinsn)
|
+ if (ifinsn)
|
+ zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
|
+ zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
|
+*/
|
+*/
|
+}
|
+}
|
+
|
+
|
|
+int zip_insn_sets_cc(rtx_insn *insn) {
|
|
+ return (get_attr_ccresult(insn)==CCRESULT_SET);
|
|
+}
|
|
+
|
|
+int zip_is_conditional(rtx_insn *insn) {
|
|
+ return (get_attr_conditional(insn)==CONDITIONAL_YES);
|
|
+}
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
|
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-12 22:10:09.239940653 -0400
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-04-21 16:49:43.785679680 -0400
|
@@ -0,0 +1,3987 @@
|
@@ -0,0 +1,4058 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: gcc/config/zip/zip.h
|
+// Filename: gcc/config/zip/zip.h
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
| Line 2867... |
Line 2915... |
+#define GCC_ZIP_H
|
+#define GCC_ZIP_H
|
+
|
+
|
+
|
+
|
+//
|
+//
|
+//
|
+//
|
+// Zip CPU configuration registers
|
+// Zip CPU configuration defines
|
+//
|
+//
|
+//
|
+//
|
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
| Line 2879... |
Line 2927... |
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
+#define ZIP_VLIW 1 // Assume we have the VLIW feature
|
+#define ZIP_VLIW 1 // Assume we have the VLIW feature
|
+#define ZIP_ATOMIC ((ZIP_PIPELINED)&&(ZIP_VLIW))
|
+#define ZIP_ATOMIC ((ZIP_PIPELINED)&&(ZIP_VLIW))
|
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
+#define ZIP_HAS_DI 1
|
+#define ZIP_HAS_DI 1
|
|
+// Should we use the peephole optimizations?
|
|
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations.
|
+
|
+
|
+// Zip has 16 registers in each user mode.
|
+// Zip has 16 registers in each user mode.
|
+// Register 15 is the program counter (PC)
|
+// Register 15 is the program counter (PC)
|
+// Register 14 is the condition codes (CC)
|
+// Register 14 is the condition codes (CC)
|
+// Register 13 is the stack pointer (SP)
|
+// Register 13 is the stack pointer (SP)
|
| Line 2953... |
Line 3003... |
+ * registers are already assumed to be used as needed.
|
+ * registers are already assumed to be used as needed.
|
+ */
|
+ */
|
+#define EPILOGUE_USES(R) (R == RETURN_ADDRESS_REGNUM)
|
+#define EPILOGUE_USES(R) (R == RETURN_ADDRESS_REGNUM)
|
+
|
+
|
+
|
+
|
+/* Normal alignment required for function parameters on the stack, in bits. All
|
|
+ * stack parameters receive at leaswt this much alignment regardless of data
|
|
+ * type. */
|
|
+#define PARM_BOUNDARY 32
|
|
+
|
|
+/* Alignment of field after 'int : 0' in a structure. */
|
|
+#define EMPTY_FIELD_BOUNDARY 32
|
|
+
|
|
+/* No data type wants to be aligned rounder than this. */
|
|
+#define BIGGEST_ALIGNMENT 32
|
|
+
|
|
+/* The best alignment to use in cases where we have a choice. */
|
+/* The best alignment to use in cases where we have a choice. */
|
+#define FASTEST_ALIGNMENT 32
|
+#define FASTEST_ALIGNMENT BITS_PER_WORD
|
+
|
|
+/* Every structures size must be a multiple of 32-bits. */
|
|
+#define STRUCTURE_SIZE_BOUNDARY 32
|
|
+
|
|
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
|
|
+ * other C compilers handle alignment of bit-fields and the structures that
|
|
+ * contain them.
|
|
+ *
|
|
+ * The behavior is that the type written for a named bit-field (int, short, or
|
|
+ * other integer type) imposes an alignment for the entire structure, as if the
|
|
+ * structure really did contain an ordinary field of that type. In addition,
|
|
+ * the bit-field is placed within the structure so that it would fit within
|
|
+ * such a field, not crossing a boundary for it.
|
|
+ *
|
|
+ * Thus, no most machines, a named bit-field whose type is written as int would
|
|
+ * not cross a four-byte boundary, and would force four-byte alignment for the
|
|
+ * whole structure. (The alignment used may not be four bytes; it is controlled
|
|
+ * by other alignment parameters.)
|
|
+ *
|
|
+ * An unnamed bit-field will not affect the alignment of the containing
|
|
+ * structure.
|
|
+ *
|
|
+ * If thhe macro is defined, its definition should be a C expression, a non
|
|
+ * zero value for the expression enables this behavior.
|
|
+ * Look at the fundamental type that is used for a bit-field and use that to
|
|
+ * impose alignment on the enclosing structure. struct s{int a:8}; should
|
|
+ * have the same alignment as 'int', not 'char'.
|
|
+ */
|
|
+#undef PCC_BITFIELD_TYPE_MATTERS
|
|
+#define PCC_BITFIELD_TYPE_MATTERS 0
|
|
+
|
+
|
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
|
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
|
+ * largest integer machine mode that should actually be used. All integer
|
+ * largest integer machine mode that should actually be used. All integer
|
+ * machine modes of this size and smaller can be used for structures and unions
|
+ * machine modes of this size and smaller can be used for structures and unions
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
+ *
|
+ *
|
+ * ZipCPU -- The default looks good enough for us.
|
+ * ZipCPU -- The default looks good enough for us.
|
+ */
|
+ */
|
+
|
+
|
+/* Make strings word-aligned so strcpy from constants will be faster. */
|
|
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) (((TREE_CODE(EXP)==STRING_CST) \
|
|
+ && ((ALIGN) < FASTEST_ALIGNMENT)) ? FASTEST_ALIGNMENT : (ALIGN))
|
|
+
|
|
+/* Make arrays of chars word-aligned for the same reasons. */
|
|
+#define DATA_ALIGNMENT(TYPE, ALIGN) ((TREE_CODE(TYPE) == ARRAY_TYPE) \
|
|
+ && (TYPE_MODE(TREE_TYPE(TYPE)) == QImode) \
|
|
+ && ((ALIGN < FASTEST_ALIGNMENT) ? FASTEST_ALIGNMENT : (ALIGN)))
|
|
+
|
|
+/* Generate Code for Profiling
|
+/* Generate Code for Profiling
|
+ */
|
+ */
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
+
|
+
|
+
|
+
|
| Line 3241... |
Line 3241... |
+ *
|
+ *
|
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
|
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
|
+ * number of bits as SImode. Therefore, one might wish to convert between the
|
+ * number of bits as SImode. Therefore, one might wish to convert between the
|
+ * two. Hence, we specify how we would do that here.
|
+ * two. Hence, we specify how we would do that here.
|
+ */
|
+ */
|
+#define POINTERS_EXTEND_UNSIGNED 0
|
+#define POINTERS_EXTEND_UNSIGNED 1
|
+
|
+
|
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
|
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
|
+ * object whose type is type and which has he specified mode and signedness is
|
+ * object whose type is type and which has he specified mode and signedness is
|
+ * to be stored in a register. This macro is only called when type is a scalar
|
+ * to be stored in a register. This macro is only called when type is a scalar
|
+ * type.
|
+ * type.
|
| Line 3285... |
Line 3285... |
+ * this should be the same as PARM_BOUNDARY.
|
+ * this should be the same as PARM_BOUNDARY.
|
+ */
|
+ */
|
+#define STACK_BOUNDARY PARM_BOUNDARY
|
+#define STACK_BOUNDARY PARM_BOUNDARY
|
+
|
+
|
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
|
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
|
|
+#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
|
+
|
+
|
+/* INCOMING_STACK_BOUNDARY
|
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary
|
|
+ * may be different from PREFERRED_STACK_BOUNDARY. This macro must evaluate
|
|
+ * to a value equal to or larger than STACK_BOUNDARY.
|
+ */
|
+ */
|
|
+#define INCOMING_STACK_BOUNDARY STACK_BOUNDARY
|
+
|
+
|
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
|
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
|
+ */
|
+ */
|
+#define FUNCTION_BOUNDARY 32
|
+#define FUNCTION_BOUNDARY 32
|
+
|
+
|
| Line 3299... |
Line 3303... |
+ * this machine, in bits. Note that this is not the biggest alignment that is
|
+ * this machine, in bits. Note that this is not the biggest alignment that is
|
+ * supported, just the biggest alignment that, when violated, may cause a fault.
|
+ * supported, just the biggest alignment that, when violated, may cause a fault.
|
+ */
|
+ */
|
+#define BIGGEST_ALIGNMENT 32
|
+#define BIGGEST_ALIGNMENT 32
|
+
|
+
|
|
+/* MALLOC_ABI_ALIGNMENT
|
|
+ */
|
|
+
|
|
+/* ATTRIBUTE_ALIGNED_VALUE
|
|
+ */
|
|
+
|
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
|
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
|
+ * given to an object that can be referenced in one operation, without
|
+ * given to an object that can be referenced in one operation, without
|
+ * disturbing any nearby object. Normally, this is BITS_PER_UNIT, but may be
|
+ * disturbing any nearby object. Normally, this is BITS_PER_UNIT, but may be
|
+ * larger on machines that don't have byte or halfword store operations.
|
+ * larger on machines that don't have byte or halfword store operations.
|
+ */
|
+ */
|
+#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT
|
+#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT
|
+
|
+
|
|
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
|
|
+ * field can require on this machine, in bits. If defined, this overrides
|
|
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
|
|
+ * alignment has been set by the __attribute__((aligned(n))) construct.
|
|
+ */
|
|
+#define BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
|
|
+
|
|
+/* ADJUST_FIELD_ALIGN
|
|
+ */
|
|
+#define ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
|
|
+
|
|
+/* MAX_STACK_ALIGNMENT
|
|
+ */
|
|
+#define MAX_STACK_ALIGNMENT BITS_PER_WORD
|
|
+
|
|
+/* MAX_OFILE_ALIGNMENT
|
|
+ */
|
|
+
|
|
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
|
|
+ * the alignment for a variable in the static store. TYPE is the data type, and
|
|
+ * BASIC-ALIGN is the alignment that the object would ordinarily have. The
|
|
+ * value of this macro is used instead of that alignment to align the object.
|
|
+ *
|
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
|
+ *
|
|
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
|
|
+ * broken. So we define it to be our fastest alignment, or 32-bits.
|
|
+ */
|
|
+#define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
|
|
+
|
|
+
|
|
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
|
|
+ */
|
|
+
|
|
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to
|
|
+ * compute the alignment given to a constant that is being placed in memory.
|
|
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object
|
|
+ * would ordinarily have. The value of this macro is used instead of that
|
|
+ * alignment to align the object.
|
|
+ *
|
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
|
+ *
|
|
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is
|
|
+ * broken. We'll define it as above.
|
|
+ *
|
|
+ */
|
|
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD
|
|
+
|
|
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
|
|
+ */
|
|
+#define LOCAL_ALIGNMENT(TYP,ALIGN) BITS_PER_WORD
|
|
+
|
|
+/* TARGET_VECTOR_ALIGNMENT
|
|
+ */
|
|
+
|
|
+/* STACK_SLOT_ALIGNMENT
|
|
+ */
|
|
+#define STACK_SLOT_ALIGNMENT(T,M,B) BITS_PER_WORD
|
|
+
|
|
+/* LOCAL_DECL_ALIGNMEN(DECL)
|
|
+ */
|
|
+#define LOCAL_DECL_ALIGNMENT(DECL) BITS_PER_WORD
|
|
+
|
|
+/* MINIMUM_ALIGNMENT
|
|
+ */
|
|
+#define MINIMUM_ALIGNMENT(EXP,MOD,ALIGN) BITS_PER_WORD
|
|
+
|
|
+/* EMPTY_FIELD_BOUNDARY
|
|
+ * Alignment of field after 'int : 0' in a structure.
|
|
+ */
|
|
+#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
|
|
+
|
|
+/* STRUCTURE_SIE_BOUNDARY
|
|
+ * ZipCPU -- Every structures size must be a multiple of 32-bits.
|
|
+ */
|
|
+#define STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD
|
|
+
|
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
|
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
|
+ * fail to work when given unaligned data. If instructions will merely go
|
+ * fail to work when given unaligned data. If instructions will merely go
|
+ * slower in that case, define this macro as 0.
|
+ * slower in that case, define this macro as 0.
|
+ *
|
+ *
|
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
|
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
|
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
|
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
|
+ * is easy, then there really are no instructions that will ever fail.
|
+ * is easy, then there really are no instructions that will ever fail.
|
+ */
|
+ */
|
+#define STRICT_ALIGNMENT 0
|
+#define STRICT_ALIGNMENT 0
|
+
|
+
|
|
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
|
|
+ * other C compilers handle alignment of bit-fields and the structures that
|
|
+ * contain them.
|
|
+ *
|
|
+ * The behavior is that the type written for a named bit-field (int, short, or
|
|
+ * other integer type) imposes an alignment for the entire structure, as if the
|
|
+ * structure really did contain an ordinary field of that type. In addition,
|
|
+ * the bit-field is placed within the structure so that it would fit within
|
|
+ * such a field, not crossing a boundary for it.
|
|
+ *
|
|
+ * Thus, no most machines, a named bit-field whose type is written as int would
|
|
+ * not cross a four-byte boundary, and would force four-byte alignment for the
|
|
+ * whole structure. (The alignment used may not be four bytes; it is controlled
|
|
+ * by other alignment parameters.)
|
|
+ *
|
|
+ * An unnamed bit-field will not affect the alignment of the containing
|
|
+ * structure.
|
|
+ *
|
|
+ * If the macro is defined, its definition should be a C expression, a non
|
|
+ * zero value for the expression enables this behavior.
|
|
+ * Look at the fundamental type that is used for a bit-field and use that to
|
|
+ * impose alignment on the enclosing structure. struct s{int a:8}; should
|
|
+ * have the same alignment as 'int', not 'char'.
|
|
+ */
|
|
+#undef PCC_BITFIELD_TYPE_MATTERS
|
|
+#define PCC_BITFIELD_TYPE_MATTERS 0
|
|
+
|
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
|
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
|
+ * largest integer machine mode that should actually be used. All integer
|
+ * largest integer machine mode that should actually be used. All integer
|
+ * machine modes of this size or smaller can be used for structures and unions
|
+ * machine modes of this size or smaller can be used for structures and unions
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * with the appropriate sizes. If this macro is undefined,
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
| Line 3594... |
Line 3708... |
+ * PC The program counter
|
+ * PC The program counter
|
+ *
|
+ *
|
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
|
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
|
+ * table pointer) are registers that we hope will not be so fixed.
|
+ * table pointer) are registers that we hope will not be so fixed.
|
+ */
|
+ */
|
|
+#ifdef DEFINE_USER_REGS
|
|
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
|
|
+#else
|
+#ifdef zip_FP_PSEUDO
|
+#ifdef zip_FP_PSEUDO
|
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1 }
|
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1 }
|
+#else
|
+#else
|
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1 }
|
+# define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1 }
|
+#endif
|
+#endif
|
|
+#endif
|
+
|
+
|
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
|
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
|
+ * that is clobbered (in general) by function calls as well as for fixed
|
+ * that is clobbered (in general) by function calls as well as for fixed
|
+ * registers. This macro therefore identifies the registers that are not
|
+ * registers. This macro therefore identifies the registers that are not
|
+ * available for general allocation of values that must live across function
|
+ * available for general allocation of values that must live across function
|
| Line 3613... |
Line 3731... |
+ * used within the function.
|
+ * used within the function.
|
+ *
|
+ *
|
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
|
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
|
+ * register above R5.
|
+ * register above R5.
|
+ */
|
+ */
|
|
+#ifdef DEFINE_USER_REGS
|
|
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
|
|
+#else
|
+#ifdef zip_FP_PSEUDO
|
+#ifdef zip_FP_PSEUDO
|
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1 }
|
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1 }
|
+#else
|
+#else
|
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1 }
|
+# define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1 }
|
+#endif
|
+#endif
|
|
+#endif
|
+
|
+
|
+/* CALL_REALLY_USED_REGISTERS ... optional macro that, if not defined, defaults
|
+/* CALL_REALLY_USED_REGISTERS ... optional macro that, if not defined, defaults
|
+ * to the value of CALL_USED_REGISTERS.
|
+ * to the value of CALL_USED_REGISTERS.
|
+ */
|
+ */
|
+
|
+
|
| Line 3629... |
Line 3751... |
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
|
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
|
+ * across a call without some part of it being clobbbered. For most machines,
|
+ * across a call without some part of it being clobbbered. For most machines,
|
+ * this macro need not be defined. It is only required for machines that do
|
+ * this macro need not be defined. It is only required for machines that do
|
+ * not preserve the entire contents of a register across a call.
|
+ * not preserve the entire contents of a register across a call.
|
+ *
|
+ *
|
+ * In the Zip CPU, we clobber R0 with our return address during a call, so let's
|
+ * ZipCPU--Always preserves the entire contents of those registers that are
|
+ * make sure this gets included here.
|
+ * preserved across calls, so this shouldnt need to be defined.
|
+ */
|
+ */
|
+#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (REGNO==0)
|
+// #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (REGNO==0)
|
+
|
+
|
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
|
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
|
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
|
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
|
+ * reg_class_contents, to take into account any dependence of these register
|
+ * reg_class_contents, to take into account any dependence of these register
|
+ * sets on target flags. The first three of these are of type char[]
|
+ * sets on target flags. The first three of these are of type char[]
|
| Line 3795... |
Line 3917... |
+ *
|
+ *
|
+ * Zip CPU has no stack-like registers, as their definition is different from
|
+ * Zip CPU has no stack-like registers, as their definition is different from
|
+ * the ZipCPU stack pointer register.
|
+ * the ZipCPU stack pointer register.
|
+ */
|
+ */
|
+
|
+
|
+#define ZIP_REG_BYTE_SIZE 1
|
+// #define ZIP_REG_BYTE_SIZE 1
|
+
|
+
|
+/* 17.08 Register Classes */
|
+/* 17.08 Register Classes */
|
+
|
+
|
+/* enum reg_class ... An enumerate type that must be defined with all the
|
+/* enum reg_class ... An enumerate type that must be defined with all the
|
+ * register class names as enumerated values. NO_REGS must be first. ALL_REGS
|
+ * register class names as enumerated values. NO_REGS must be first. ALL_REGS
|
| Line 3824... |
Line 3946... |
+
|
+
|
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
|
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
|
+ * classes as C string constants. These names are used in writing some of the
|
+ * classes as C string constants. These names are used in writing some of the
|
+ * debugging dumps.
|
+ * debugging dumps.
|
+ */
|
+ */
|
|
+#ifdef DEFINE_USER_REGS
|
|
+# define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
|
|
+#else
|
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
|
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
|
|
+#endif
|
+
|
+
|
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
|
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
|
+ * classes, as integerss which are bit masks. The nth integer specifies the
|
+ * classes, as integers which are bit masks. The nth integer specifies the
|
+ * contents of class n. That way the integer mask is interpreted as that
|
+ * contents of class n. That way the integer mask is interpreted as that
|
+ * register r is in the class if (mask&(1<<r)) is 1.
|
+ * register r is in the class if (mask&(1<<r)) is 1.
|
+ *
|
+ *
|
+ * When the machine has more than 32 registers ... that's not us.
|
+ * When the machine has more than 32 registers ... that's not us.
|
+ *
|
+ *
|
+ * ZipCPU --- This is straight forward, three register classes, etc.
|
+ * ZipCPU --- This is straight forward, three register classes, etc.
|
+ */
|
+ */
|
|
+#ifdef DEFINE_USER_REGS
|
|
+# define REG_CLASS_CONTENTS { { 0x000000000}, {0x00003fff}, {0x0ffff0000l}, {0x0ffffffffl} }
|
|
+#else
|
+#ifdef zip_FP_PSEUDO
|
+#ifdef zip_FP_PSEUDO
|
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x13fff}, {0x1ffff} }
|
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x13fff}, {0x1ffff} }
|
+#else
|
+#else
|
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x03fff}, {0x0ffff} }
|
+#define REG_CLASS_CONTENTS { { 0x00000}, {0x03fff}, {0x0ffff} }
|
+#endif
|
+#endif
|
+
|
|
+#ifdef DEFINE_USER_REGS
|
|
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
|
|
+#define REG_CLASS_CONTENTS { { 0x00000},{0x03fff},{0x0ffff0000},{0x0ffffffff} }
|
|
+#define FIXED_REGISTERS { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
|
|
+#define CALL_USED_REGISTERS { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1, 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
|
|
+#endif
|
+#endif
|
+
|
+
|
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
|
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
|
+ * containing hard register REGNO. In general there is more than one such
|
+ * containing hard register REGNO. In general there is more than one such
|
+ * class; Choose a class which is minimal, meaning that no smaller class also
|
+ * class; Choose a class which is minimal, meaning that no smaller class also
|
| Line 3898... |
Line 4021... |
+
|
+
|
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
|
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
|
+ * number num is suitable for use as a base register in operand addresses.
|
+ * number num is suitable for use as a base register in operand addresses.
|
+ */
|
+ */
|
+#undef REGNO_OK_FOR_BASE_P
|
+#undef REGNO_OK_FOR_BASE_P
|
+#ifdef DEFINE_USER_REGS
|
+# define REGNO_OK_FOR_BASE_P(NUM) ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC))
|
+# define REGNO_OK_FOR_BASE_P(NUM) ((NUM != zip_CC)&&(NUM < 16))
|
|
+#else
|
|
+# define REGNO_OK_FOR_BASE_P(NUM) (NUM != zip_CC)
|
|
+#endif
|
|
+
|
+
|
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
|
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
|
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
|
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
|
+ * memory reference in MODE. You should define this macro if the mode of the
|
+ * memory reference in MODE. You should define this macro if the mode of the
|
+ * memory reference affects whether a register may be used as a base register.
|
+ * memory reference affects whether a register may be used as a base register.
|
| Line 6815... |
Line 6934... |
+
|
+
|
+#endif /* GCC_ZIP_H */
|
+#endif /* GCC_ZIP_H */
|
+
|
+
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
|
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-12 21:02:20.294810924 -0400
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-21 20:01:08.790659796 -0400
|
@@ -0,0 +1,2422 @@
|
@@ -0,0 +1,2961 @@
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
+;; Filename: zip.md
|
+;; Filename: zip.md
|
+;;
|
+;;
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
| Line 6895... |
Line 7014... |
+ (UNSPEC_RESTORE_CONTEXT 6)
|
+ (UNSPEC_RESTORE_CONTEXT 6)
|
+ (UNSPEC_BITREV 7)
|
+ (UNSPEC_BITREV 7)
|
+ (UNSPEC_GETUCC 8)
|
+ (UNSPEC_GETUCC 8)
|
+ (UNSPEC_GETCC 9)
|
+ (UNSPEC_GETCC 9)
|
+ (UNSPEC_LDILO 10)
|
+ (UNSPEC_LDILO 10)
|
|
+ ; (UNSPEC_RAW_CALL 11)
|
+ ])
|
+ ])
|
+;
|
+;
|
+;
|
+;
|
+; Registers by name
|
+; Registers by name
|
+(define_constants
|
+(define_constants
|
| Line 7243... |
Line 7363... |
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;
|
+;;
|
|
+;; Substitution Pattern
|
|
+;;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;
|
|
+;
|
|
+(define_subst "cc_substitution"
|
|
+ ; The pattern may not have any match_dup expressions.
|
|
+ [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ [(set (match_dup 0) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
|
|
+ ])
|
|
+;
|
|
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
|
|
+;
|
|
+;
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
+;;
|
+;; General arithmetic instructions
|
+;; General arithmetic instructions
|
+;;
|
+;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
|
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
|
+ ])
|
+ ]) ])
|
+(define_insn_and_split "add<mode>3_split_reg"
|
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#" ; This code means the instruction *must* be split
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "predicable" "yes")])
|
|
+(define_insn_and_split "add<mode>3_split_off"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#" ; This code means the instruction *must* be split
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "predicable" "yes")])
|
|
+(define_insn "addsi3_reg_clobber"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ADD %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "addsi3_reg_raw"
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "ADD %2,%0"
|
+ "ADD %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "add<mode>3_off" ; Fastest/best instruction always goes first
|
+(define_insn "add<mode>3_off_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "ADD %3+%2,%0"
|
+ "ADD %3+%2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "add<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ADD %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+(define_expand "sub<mode>3"
|
+(define_expand "sub<mode>3"
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
|
+(define_insn "sub<mode>3_reg"
|
+(define_insn_and_split "sub<mode>3_split_reg"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_reg_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "SUB %2,%0"
|
+ "SUB %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "sub<mode>3_off"
|
+(define_insn "sub<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "SUB %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "sub<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_off_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "SUB %3+%2,%0"
|
+ "SUB %3+%2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "sub<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "SUB %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "mul<mode>3"
|
+(define_insn "mul<mode>3"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
+ (clobber (match_scratch:ZI 3 "=r"))
|
+ (clobber (match_scratch:ZI 3 "=r"))
|
| Line 7412... |
Line 7632... |
+ ]
|
+ ]
|
+ ""
|
+ ""
|
+ "CMP %0,%2
|
+ "CMP %0,%2
|
+ MOV.LT %2,%0"
|
+ MOV.LT %2,%0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;
|
|
+;
|
+(define_expand "and<mode>3"
|
+(define_expand "and<mode>3"
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
|
+(define_insn_and_split "and<mode>3_reg_split"
|
+(define_insn "and<mode>3_reg"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_reg_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "AND %2,%0"
|
+ "AND %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "and<mode>3_off"
|
+(define_insn "and<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "and<mode>3_off_split"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
+ ""
|
+ "AND %3+%2,%0"
|
+ "#"
|
+ [(set_attr "ccresult" "set")])
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_off_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
|
+ ""
|
|
+ "AND %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "and<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "AND %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
+(define_expand "ior<mode>3"
|
+(define_expand "ior<mode>3"
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
|
+(define_insn_and_split "ior<mode>3_reg_split"
|
+(define_insn "ior<mode>3_reg"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_reg_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "OR %2,%0"
|
+ "OR %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "ior<mode>3_off"
|
+(define_insn "ior<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "OR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "ior<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_off_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "OR %3+%2,%0"
|
+ "OR %3+%2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ior<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "OR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+;
|
+(define_expand "xor<mode>3"
|
+(define_expand "xor<mode>3"
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
+ "")
|
+ "")
|
+(define_insn "xor<mode>3_reg"
|
+(define_insn_and_split "xor<mode>3_reg_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_reg_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "XOR %2,%0"
|
+ "XOR %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "xor<mode>3_off"
|
+(define_insn "xor<mode>3_reg_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "XOR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn_and_split "xor<mode>3_off_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1)
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_off_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "XOR %3+%2,%0"
|
+ "XOR %3+%2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "xor<mode>3_off_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "XOR %3+%2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
+;(define_insn "addv<mode>4"
|
+;(define_insn "addv<mode>4"
|
+ ;[(set (match_operand:ZI 0 "register_operand" "=r")
|
+ ;[(set (match_operand:ZI 0 "register_operand" "=r")
|
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
|
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
|
+ ;(match_operand:ZI 2 "general_operand" "rO")))
|
+ ;(match_operand:ZI 2 "general_operand" "rO")))
|
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
| Line 7507... |
Line 7855... |
+;; BC %3
|
+;; BC %3
|
+;;
|
+;;
|
+;; (define_insn "umulvsi4"
|
+;; (define_insn "umulvsi4"
|
+;; ... ???)
|
+;; ... ???)
|
+;;
|
+;;
|
+(define_insn "ashr<mode>3"
|
+(define_expand "ashr<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "ashr<mode>3_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashr<mode>3_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "ASR %2,%0"
|
+ "ASR %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "ashl<mode>3"
|
+(define_insn "ashr<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ASR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "ashl<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "ashl<mode>3_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "ashl<mode>3_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "LSL %2,%0"
|
+ "LSL %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "lshr<mode>3"
|
+(define_insn "ashl<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "LSL %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "lshr<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "lshr<mode>3_split"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "register_operand" "rR")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "lshr<mode>3_raw"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "LSR %2,%0"
|
+ "LSR %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_insn "rotl<mode>3"
|
+(define_insn "lshr<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "LSR %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
|
+(define_expand "rotl<mode>3"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
|
+(define_insn_and_split "rotl<mode>3_split"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
|
+ ""
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2)))
|
|
+ (clobber (reg:CC CC_REG))])]
|
|
+ ""
|
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "rotl<mode>3_raw"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ ""
|
+ "ROL %2,%0"
|
+ "ROL %2,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
|
+(define_insn "rotl<mode>3_clobber"
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
|
+ (clobber (reg:CC CC_REG))]
|
|
+ ""
|
|
+ "ROL %2,%0"
|
|
+ [(set_attr "ccresult" "set")])
|
|
+;
|
|
+;
|
+;
|
+;
|
+(define_insn "neg<mode>2"
|
+(define_insn "neg<mode>2"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (clobber (reg:CC CC_REG))]
|
+ (clobber (reg:CC CC_REG))]
|
| Line 7565... |
Line 8013... |
+ "POPC %1,%0"
|
+ "POPC %1,%0"
|
+ [(set_attr "ccresult" "set")])
|
+ [(set_attr "ccresult" "set")])
|
+(define_expand "parity<mode>2"
|
+(define_expand "parity<mode>2"
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (clobber (reg:CC CC_REG))])
|
+ (parallel [
|
+ (parallel [
|
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
|
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ])
|
+ ])
|
+(define_insn "one_cmpl<mode>2"
|
+(define_insn "one_cmpl<mode>2"
|
| Line 7630... |
Line 8078... |
+ "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
|
+ "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
|
+ INTVAL(XEXP(operands[0],1)),
|
+ INTVAL(XEXP(operands[0],1)),
|
+ INTVAL(XEXP(operands[0],1)+1));
|
+ INTVAL(XEXP(operands[0],1)+1));
|
+ return buf;
|
+ return buf;
|
+ }
|
+ }
|
+ } else return "BREAK";
|
+ } return "BREAK";
|
+ }
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+(define_insn "movdi_ldi"
|
+(define_insn "movdi_ldi"
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
+ (match_operand:DI 1 "immediate_operand" "i"))]
|
+ (match_operand:DI 1 "immediate_operand" "i"))]
|
| Line 7968... |
Line 8416... |
+ (const_int 1) (const_int 0)))]
|
+ (const_int 1) (const_int 0)))]
|
+ ""
|
+ ""
|
+ { return (zip_set_zero_or_one(operands[1], operands[0]));
|
+ { return (zip_set_zero_or_one(operands[1], operands[0]));
|
+ }
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+(define_insn "mov<mode>cc"
|
+(define_expand "mov<mode>cc"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
+ (if_then_else:ZI (match_operand 1 "comparison_operator")
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (match_operand:ZI 2 "general_operand" "rio")
|
+ (match_operand:ZI 2 "general_operand" "rio")
|
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))]
|
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))]
|
+ ""
|
+ ""
|
+ {
|
+ {
|
+ return zip_movsicc(operands[0], operands[1], operands[2], operands[3]);
|
+ zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]);
|
+ }
|
+ DONE;
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ })
|
|
+(define_insn_and_split "movsicc_bare"
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
|
+ (if_then_else (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (match_operand:SI 2 "general_operand" "rio")
|
|
+ (match_operand:SI 3 "register_operand" "0")))]
|
|
+ "(zip_supported_condition(GET_CODE(operands[1])))"
|
|
+ "#"
|
|
+ "(reload_completed)"
|
|
+ [(cond_exec (match_operator 1 "ordered_comparison_operator"
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
|
+ (set (match_dup 0) (match_dup 2)))]
|
|
+ "" [(set_attr "predicable" "no")])
|
+(define_insn "add<mode>cc"
|
+(define_insn "add<mode>cc"
|
+ [(set (match_operand:ZI 0 "register_operand" "=r,r")
|
+ [(set (match_operand:ZI 0 "register_operand" "=r,r")
|
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ [(reg:CC CC_REG) (const_int 0)])
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
|
| Line 7993... |
Line 8453... |
+ return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
|
+ return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
|
+ }
|
+ }
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+;
|
+;
|
+;
|
+;
|
+;(define_expand "mov<mode>cc"
|
|
+; [(set (match_operand:ZI 0 "general_operand" "=rm,rm,r,r,r"
|
|
+; (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
|
+; [(reg:CC CC_REG) (const_int 0)])
|
|
+; (match_operand:ZI 2 "general_operand" "0,r,0,m,rm")
|
|
+; (match_operand:ZI 3 "general_operand" "r,0,m,0,rm"))))]
|
|
+; )
|
|
+;
|
|
+;
|
|
+;
|
+;
|
+; While an interesting approach, the following suffers from problems when the
|
+; While an interesting approach, the following suffers from problems when the
|
+; move amount is constant. At anything less than four, moves should not require
|
+; move amount is constant. At anything less than four, moves should not require
|
+; the movmemSI instruction. At anything greater, if constant, the initial tests
|
+; the movmemSI instruction. At anything greater, if constant, the initial tests
|
+; are not required and should result in a hardcoded result. Practically,
|
+; are not required and should result in a hardcoded result. Practically,
|
+; though, this should really be a define_expand instruction, calling on the
|
+; though, this should really be a define_expand instruction, calling on the
|
+; RTX's of all the respective subinstructions found below.
|
+; RTX's of all the respective subinstructions found below. Or, perhaps, it is
|
|
+; better as a subroutine?
|
+;
|
+;
|
+;(define_insn "movmemSI"
|
+;(define_insn "movmemSI"
|
+; [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
|
+; [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
|
+; (mem:BLK (match_operand 1 "register_operand" "+r")));Src
|
+; (mem:BLK (match_operand 1 "register_operand" "+r")));Src
|
+; (use (match_operand:SI 2 "register_operand" "+r"))]); Length
|
+; (use (match_operand:SI 2 "register_operand" "+r"))]); Length
|
| Line 8085... |
Line 8537... |
+;
|
+;
|
+;
|
+;
|
+(define_expand "jump"
|
+(define_expand "jump"
|
+ [(set (pc)
|
+ [(set (pc)
|
+ (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
|
+ (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
|
+(define_insn "jump_const" ; Must be modeless, VOIDmode, not SI or any othr
|
+(define_insn "jump_const"
|
+ [(set (pc) ; Otherwise it won't accept jumps to labels
|
+ [(set (pc)
|
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))]
|
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))]
|
+ ""
|
+ ""
|
+ "BRA %0"
|
+ "BRA %0"
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
+(define_insn "jump_label" ; Must be modeless, VOIDmode, not SI or any othr
|
+(define_insn "jump_label" ; Must be modeless, VOIDmode, not SI or any othr
|
| Line 8309... |
Line 8761... |
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))
|
+ (pc)))
|
+ ;(clobber (reg:CC CC_REG))
|
+ ;(clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "" ; Flip the condition, and then we can jump
|
+ "" ; Flip the condition, and then we can jump
|
+ "XOR\t2,CC
|
+ "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
|
+ BC\t%0"
|
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
+ (set_attr "conditional" "yes")
|
+ (set_attr "ccresult" "unknown")])
|
+ (set_attr "ccresult" "unknown")])
|
+(define_insn "cbranch_jmp_leu"
|
+(define_insn "cbranch_jmp_leu"
|
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
| Line 8330... |
Line 8781... |
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (label_ref (match_operand 0 "" ""))
|
+ (pc)))
|
+ (pc)))
|
+ ;(clobber (reg:CC CC_REG))
|
+ ;(clobber (reg:CC CC_REG))
|
+ ]
|
+ ]
|
+ "" ; Flip the comparison, then check for GEU (once flipped)a
|
+ ""
|
+ ; Z is naturally checked for, as C would've never been set on Z
|
+ "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
|
+ ; so by flipping it, it is tantamount to saying Z or GTU.
|
|
+ "BZ\t%0
|
|
+ XOR\t2,CC
|
|
+ BC\t%0"
|
|
+ [(set_attr "predicable" "no")
|
+ [(set_attr "predicable" "no")
|
+ (set_attr "conditional" "yes")
|
+ (set_attr "conditional" "yes")
|
+ (set_attr "ccresult" "unknown")])
|
+ (set_attr "ccresult" "unknown")])
|
+(define_insn "cbranchdi4"
|
+(define_insn "cbranchdi4"
|
+ [(set (pc) (if_then_else
|
+ [(set (pc) (if_then_else
|
| Line 8908... |
Line 9355... |
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 "register_operand")))
|
+ (match_operand:SI 1 "register_operand")))
|
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 2 ""))
|
+ (label_ref (match_operand 2 ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_dup 2))
|
+ (label_ref (match_dup 2))
|
+ (pc)))]
|
+ (pc)))]
|
+ "")
|
+ "")
|
|
+(define_peephole2
|
|
+ [(match_scratch:SI 3 "=r")
|
|
+ (set (reg:CC CC_REG) (compare:CC
|
|
+ (match_operand:SI 0 "register_operand")
|
|
+ (match_operand 1 "const_int_operand")))
|
|
+ (match_dup 3)
|
|
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 2 ""))
|
|
+ (pc)))]
|
|
+ "(ZIP_PEEPHOLE)"
|
|
+ [(set (match_dup 3) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))
|
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_dup 2))
|
|
+ (pc)))]
|
|
+ "")
|
|
+;(define_peephole2
|
|
+; [(set (reg:CC CC_REG) (compare:CC
|
|
+; (match_operand:SI 0 "register_operand")
|
|
+; (match_operand 1 "const_int_operand")))
|
|
+; (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_operand 2 ""))
|
|
+; (pc)))]
|
|
+; ""
|
|
+; [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
|
+; (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_dup 2))
|
|
+; (pc)))]
|
|
+; "operands[1] = GEN_INT(INTVAL(operands[1])-1);")
|
+;
|
+;
|
+;
|
+;
|
+; Match:
|
+; Match:
|
+; CMP R1,R0
|
+; CMP R1,R0
|
+; BGEU lbl
|
+; BGEU lbl
|
| Line 8930... |
Line 9406... |
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 "register_operand")))
|
+ (match_operand:SI 1 "register_operand")))
|
+ (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 2 ""))
|
+ (label_ref (match_operand 2 ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ [(set (reg:CC CC_REG) (compare:CC
|
+ (match_dup 1) (plus (match_dup 0) (const_int 1))))
|
+ (match_dup 1) (plus (match_dup 0) (const_int 1))))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_dup 2))
|
+ (label_ref (match_dup 2))
|
+ (pc)))]
|
+ (pc)))]
|
| Line 8953... |
Line 9429... |
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 "register_operand")))
|
+ (match_operand:SI 1 "register_operand")))
|
+ (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 2 ""))
|
+ (label_ref (match_operand 2 ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1)
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1)
|
+ (plus:SI (match_dup 0) (const_int 1))))
|
+ (plus:SI (match_dup 0) (const_int 1))))
|
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_dup 2))
|
+ (label_ref (match_dup 2))
|
+ (pc)))]
|
+ (pc)))]
|
| Line 8976... |
Line 9452... |
+ (match_operand:SI 0 "register_operand" "")
|
+ (match_operand:SI 0 "register_operand" "")
|
+ (match_operand:SI 1 "register_operand" "")))
|
+ (match_operand:SI 1 "register_operand" "")))
|
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_operand 2 "" ""))
|
+ (label_ref (match_operand 2 "" ""))
|
+ (pc)))]
|
+ (pc)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
+ (plus (match_dup 1) (const_int 1))))
|
+ (plus (match_dup 1) (const_int 1))))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
+ (label_ref (match_dup 2))
|
+ (label_ref (match_dup 2))
|
+ (pc)))]
|
+ (pc)))]
|
+ "")
|
+ "")
|
+;
|
+;
|
+; I need to revisit these peephole optimizations when I can come up with another
|
+(define_peephole2
|
+; way of adding one to the constant integer. The approach listed below just
|
+ [(set (reg:CC CC_REG)
|
+; ... doesn't work.
|
+ (compare:CC (match_operand:SI 0 "register_operand" "")
|
|
+ (match_operand:SI 1 "const_int_operand" "")))
|
|
+ (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 2 "" ""))
|
|
+ (pc)))]
|
|
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
|
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_dup 2))
|
|
+ (pc)))]
|
|
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
|
|
+(define_peephole2
|
|
+ [(set (reg:CC CC_REG)
|
|
+ (compare:CC (match_operand:SI 0 "register_operand" "")
|
|
+ (match_operand:SI 1 "const_int_operand" "")))
|
|
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_operand 2 "" ""))
|
|
+ (pc)))]
|
|
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
|
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
|
+ (label_ref (match_dup 2))
|
|
+ (pc)))]
|
|
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
|
+;
|
+;
|
+;(define_peephole2
|
|
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "")
|
|
+; (match_operand:SI 1 "const_int_operand" "")))
|
|
+; (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_operand 2 "" ""))
|
|
+; (pc)))]
|
|
+; "(INTVAL(operands[1])<((1<<17)-2))"
|
|
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
|
|
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_dup 2))
|
|
+; (pc)))]
|
|
+; "")
|
|
+;(define_peephole2
|
|
+; [(set (reg:CC CC_REG) (compare (match_operand:SI 0 "register_operand" "")
|
|
+; (match_operand:SI 1 "const_int_operand" "")))
|
|
+; (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_operand 2 "" ""))
|
|
+; (pc)))]
|
|
+; "(INTVAL(operands[1])<((1<<17)-2))"
|
|
+; [(set (reg:CC CC_REG) (compare (match_dup 0) (plus (match_dup 1) (const_int 1))))
|
|
+; (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
|
+; (label_ref (match_dup 2))
|
|
+; (pc)))]
|
|
+; "")
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
|
+; Match:
|
|
+; (parallel [(set () ()) (clobber (CC))])
|
|
+; (compare () ())
|
|
+; Transform to:
|
|
+; (parallel [(set () ()) (set (CC) (0))]
|
|
+; (compare () ())
|
|
+;
|
|
+(define_peephole2
|
|
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
|
|
+ (clobber (reg:CC CC_REG))])
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "")
|
|
+ (match_operand:SI 3 "")))]
|
|
+ "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)"
|
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))]
|
|
+ "")
|
|
+;
|
|
+;
|
|
+;
|
|
+; Match:
|
|
+; (parallel [(set () ()) (clobber (CC))])
|
|
+; (set () ())
|
|
+; (compare () ())
|
|
+; Transform to:
|
|
+; (parallel [(set () ()) (set (CC) (0))]
|
|
+; (set () ())
|
|
+; (compare () ())
|
|
+;
|
|
+(define_peephole2
|
|
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
|
|
+ (clobber (reg:CC CC_REG))])
|
|
+ (set (match_operand 2 "") (match_operand 3 ""))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "")
|
|
+ (match_operand:SI 5 "")))]
|
|
+ "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))"
|
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ (set (match_dup 2) (match_dup 3))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))]
|
|
+ "")
|
|
+;
|
|
+;
|
+;
|
+;
|
+; Match:
|
+; Match:
|
+; MOV A(R1),R3
|
+; MOV A(R1),R3
|
+; CMP R3,R0
|
+; CMP R3,R0
|
+; (R3 is dead)
|
+; (R3 is dead)
|
| Line 9030... |
Line 9548... |
+ (plus:SI (match_operand:SI 1 "register_operand")
|
+ (plus:SI (match_operand:SI 1 "register_operand")
|
+ (match_operand:SI 2 "zip_mvimm_operand_p")))
|
+ (match_operand:SI 2 "zip_mvimm_operand_p")))
|
+ (set (reg:CC CC_REG)
|
+ (set (reg:CC CC_REG)
|
+ (compare:CC (match_operand:SI 0 "register_operand")
|
+ (compare:CC (match_operand:SI 0 "register_operand")
|
+ (match_dup 3)))]
|
+ (match_dup 3)))]
|
+ "peep2_regno_dead_p(2, REGNO(operands[3]))"
|
+ "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))"
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
+ (plus:SI (match_dup 1) (match_dup 2))))]
|
+ (plus:SI (match_dup 1) (match_dup 2))))]
|
+ "")
|
+ "")
|
+;
|
+;
|
+;
|
+;
|
| Line 9047... |
Line 9565... |
+(define_peephole2
|
+(define_peephole2
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 ""))
|
+ (match_operand:SI 1 ""))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ])
|
+ ])
|
+;
|
+;
|
+;
|
+;
|
+; Match:
|
+; Match:
|
+; ALU OpB,R0
|
+; ALU OpB,R0
|
+; MOV R1,R2 // Can be LDI, LOD, STO, etc.
|
+; MOV R1,R2 // Can be LDI, LOD, STO, etc.
|
+; CMP 0,R1
|
+; CMP 0,R0
|
+; Transform to:
|
+; Transform to:
|
+; ALU OpB,R0
|
+; ALU OpB,R0
|
+; MOV R0,R1
|
+; MOV R0,R1
|
+;
|
+;
|
+(define_peephole2
|
+(define_peephole2
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 ""))
|
+ (match_operand:SI 1 ""))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
|
+ (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
+ "(!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG)))"
|
+ "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))"
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_dup 2) (match_dup 3))
|
+ (set (match_dup 2) (match_dup 3))
|
+ ])
|
+ ])
|
+;
|
+;
|
| Line 9088... |
Line 9606... |
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 ""))
|
+ (match_operand:SI 1 ""))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))
|
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
|
+ ""
|
+ "(ZIP_PEEPHOLE)"
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_dup 2) (match_dup 3))
|
+ (set (match_dup 2) (match_dup 3))
|
+ ])
|
+ ])
|
+;
|
+;
|
+;
|
+;
|
+; Match:
|
+; Match:
|
+; MOV A(R0),R0
|
|
+; ADD $x,R1
|
|
+; (CCREG is dead, and (A+x) is within range ...)
|
|
+; Transform to:
|
|
+; MOV (A+$x)(R1),R0
|
|
+; ... how do I do the plus? Let's build it with a plus of zero, and work from
|
|
+; there
|
|
+; MOV R1,R0
|
+; MOV R1,R0
|
+; ADD $x,R0
|
+; ADD $x,R0
|
+; (CCREG is dead, and x is within range ...)
|
+; (CCREG is dead, and x is within range ...)
|
+; Transform to:
|
+; Transform to:
|
+; MOV (A+$x)(R1),R0
|
+; MOV $x(R1),R0
|
+(define_peephole2
|
+(define_peephole2
|
+ [(set (match_operand:SI 0 "register_operand")
|
+ [(set (match_operand:SI 0 "register_operand")
|
+ (match_operand:SI 1 "register_operand"))
|
+ (match_operand:SI 1 "register_operand"))
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
|
+ (match_operand 2 "zip_mvimm_operand_p")))
|
+ (match_operand 2 "zip_mvimm_operand_p")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ]
|
+ ]
|
+ "(peep2_regno_dead_p(2,CC_REG))"
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))"
|
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
|
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
|
+;
|
+;
|
|
+; Match:
|
|
+; MOV A(R0),R0
|
|
+; ADD $x,R1
|
|
+; (CCREG is dead, and (A+x) is within range ...)
|
|
+; Transform to:
|
|
+; MOV $x(R1),R0
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:SI 0 "register_operand")
|
|
+ (plus:SI (match_operand:SI 1 "register_operand")
|
|
+ (match_operand 2 "zip_mvimm_operand_p")))
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
|
|
+ (match_operand 3 "zip_mvimm_operand_p")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ ]
|
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
|
|
+ &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17)))
|
|
+ &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))"
|
|
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
|
|
+ "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));")
|
|
+;
|
+;
|
+;
|
+;
|
+;
|
+; Match:
|
+; Match:
|
+; ADD $x,R0
|
+; ADD $x,R0
|
+; MOV R0,R1
|
+; MOV R0,R1
|
| Line 9134... |
Line 9666... |
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
+ (plus:SI (match_dup 0)
|
+ (plus:SI (match_dup 0)
|
+ (match_operand 1 "zip_mvimm_operand_p")))
|
+ (match_operand 1 "zip_mvimm_operand_p")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))]
|
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))]
|
+ "(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
|
+ [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
|
+ [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
|
+;
|
+;
|
+;
|
+;
|
|
+;
|
|
+; Match:
|
|
+; ADD $x,R0
|
|
+; MOV A(R0),R1
|
|
+; (CCREG is dead, and R0 is dead)
|
|
+; Transform to:
|
|
+; MOV (A+$x)(R0),R1
|
|
+;
|
|
+(define_peephole2
|
|
+ [(parallel [
|
|
+ (set (match_operand:SI 0 "register_operand")
|
|
+ (plus:SI (match_dup 0)
|
|
+ (match_operand 1 "zip_mvimm_operand_p")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ (set (match_operand:SI 2 "register_operand")
|
|
+ (plus:SI (match_dup 0)
|
|
+ (match_operand 3 "zip_mvimm_operand_p")))
|
|
+ ]
|
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
|
|
+ &&(peep2_regno_dead_p(1,REGNO(operands[0])))
|
|
+ &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17)))
|
|
+ &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))"
|
|
+ [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
|
|
+ "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));")
|
|
+;
|
|
+;
|
|
+;
|
+; Match:
|
+; Match:
|
+; ADD $x,R0
|
+; ADD $x,R0
|
+; ADD R0,Rn
|
+; ADD R0,Rn
|
+; (R0 is dead, if R0 is not Rn)
|
+; (R0 is dead, if R0 is not Rn)
|
+; Transform to:
|
+; Transform to:
|
| Line 9154... |
Line 9713... |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (parallel [(set (match_operand:SI 2 "register_operand")
|
+ (parallel [(set (match_operand:SI 2 "register_operand")
|
+ (plus:SI (match_dup 2) (match_dup 0)))
|
+ (plus:SI (match_dup 2) (match_dup 0)))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
+ ]
|
+ ]
|
+ "(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
+ [(parallel [(set (match_dup 2)
|
+ [(parallel [(set (match_dup 2)
|
+ (plus:SI (match_dup 2)
|
+ (plus:SI (match_dup 2)
|
+ (plus:SI (match_dup 0)
|
+ (plus:SI (match_dup 0)
|
+ (match_dup 1))))
|
+ (match_dup 1))))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
| Line 9178... |
Line 9737... |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (match_operand:SI 3 "register_operand")
|
+ (set (match_operand:SI 3 "register_operand")
|
+ (mem:SI (plus:SI (match_dup 0)
|
+ (mem:SI (plus:SI (match_dup 0)
|
+ (match_operand 2 "zip_opb_immv_p"))))
|
+ (match_operand 2 "zip_opb_immv_p"))))
|
+ ]
|
+ ]
|
+ "(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
|
+ [(set (match_dup 3) (mem:SI (match_dup 0)))
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ ])
|
|
+(define_peephole2
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
|
+ (plus:SI (match_dup 0)
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
|
+ (clobber (reg:CC CC_REG))])
|
|
+ (set (match_operand:SI 3 "register_operand")
|
|
+ (mem:SI (plus:SI (match_dup 0)
|
|
+ (match_operand 2 "zip_opb_immv_p"))))
|
|
+ ]
|
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
+ [(set (match_dup 3) (mem:SI (match_dup 0)))
|
+ [(set (match_dup 3) (mem:SI (match_dup 0)))
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ])
|
+ ])
|
+;
|
+;
|
| Line 9201... |
Line 9774... |
+ (match_operand 1 "zip_opb_immv_p")))
|
+ (match_operand 1 "zip_opb_immv_p")))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
|
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
|
+ (match_operand:SI 3 "register_operand"))
|
+ (match_operand:SI 3 "register_operand"))
|
+ ]
|
+ ]
|
+ "(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
|
+ [(set (mem:SI (match_dup 0)) (match_dup 3))
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ ])
|
|
+(define_peephole2
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
|
+ (plus:SI (match_dup 0)
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
|
+ (clobber (reg:CC CC_REG))])
|
|
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
|
|
+ (match_operand:SI 3 "register_operand"))
|
|
+ ]
|
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
+ [(set (mem:SI (match_dup 0)) (match_dup 3))
|
+ [(set (mem:SI (match_dup 0)) (match_dup 3))
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
+ ])
|
+ ])
|
+;
|
+;
|
| Line 9219... |
Line 9805... |
+; ANY R1,R2
|
+; ANY R1,R2
|
+; ADD $x(R0),Rn
|
+; ADD $x(R0),Rn
|
+;
|
+;
|
+;
|
+;
|
+;
|
+;
|
+; Need a peephole optimizer (not peephole2) for
|
+; Match:
|
+; [(call ...
|
+; MOV R1,R0
|
+; (set (pc) (label))]
|
+; AND #/R2,R0
|
+; To result with
|
+; (Ry dead ...)
|
+; "MOV\tlabel,R0
|
+; Transform to:
|
+; JMP\tsubroutine"
|
+; TEST #/Rz,Rx
|
|
+;
|
|
+(define_peephole2
|
|
+ [(set (match_operand:SI 0 "register_operand")
|
|
+ (match_operand:SI 1 "register_operand"))
|
|
+ (parallel [(set (match_dup 0)
|
|
+ (and:SI (match_dup 0)
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p")))
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
|
+ ]
|
|
+ "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
|
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2))
|
|
+ (const_int 0)))])
|
|
+;
|
|
+; Match:
|
|
+; (call ...
|
|
+; (set (pc) (label))
|
|
+; or (in asm)
|
|
+; MOV .Lcallx(PC),R0
|
|
+; BRA (somewhere)
|
|
+; .Lcallx
|
|
+; BRA (somewhere-else)
|
|
+; Transform to:
|
|
+;
|
|
+; (sequence [(call ...
|
|
+; (set (pc) (label))])
|
|
+; or (in asm)
|
|
+; "LDI (somewhere-else),R0
|
|
+; BRA subroutine"
|
|
+;
|
|
+; While the following looks good, it doesnt work. My guess is that the reason
|
|
+; why it doesnt work is that the jump at the end crosses basic block boundaries.
|
|
+;
|
|
+;(define_insn "void_call_mem_unspec"
|
|
+; [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL)
|
|
+; (match_operand 1 "const_int_operand" "n"))
|
|
+; (clobber (reg:SI RTN_REG))
|
|
+; (clobber (reg:CC CC_REG))]
|
|
+; ""
|
|
+; "BRA\t%0,PC"
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
|
+;(define_peephole2
|
|
+; [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))
|
|
+; (match_operand 1 "const_int_operand"))
|
|
+; (clobber (reg:SI RTN_REG))
|
|
+; (clobber (reg:CC CC_REG))])
|
|
+; ; The match operand for the (set (pc) ...) cannot have anything but
|
|
+; ; VOIDmode, or it wont match.
|
|
+; (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))]
|
|
+; ""
|
|
+; [(set (reg:SI RTN_REG) (match_dup 2))
|
|
+; (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL)
|
|
+; (match_operand 1 "const_int_operand"))
|
|
+; (use (reg:SI RTN_REG))
|
|
+; (clobber (reg:SI RTN_REG))
|
|
+; (clobber (reg:CC CC_REG))]
|
|
+; "fprintf(stderr, \"CALL-JUMP Matched\");")
|
|
+;
|
|
+;
|
|
+;
|
|
+; So, the following *should* have worked as well. However, this falls apart
|
|
+; because the 'final' routine can't tell if we are calling a subroutine in this
|
|
+; function or not.
|
|
+;
|
|
+;(define_peephole
|
|
+ ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p"))
|
|
+ ;(match_operand 1 "const_int_operand"))
|
|
+ ;(clobber (reg:SI RTN_REG))
|
|
+ ;(clobber (reg:CC CC_REG))])
|
|
+ ;(set (pc) (label_ref (match_operand 2 "")))]
|
|
+ ;""
|
|
+ ;"LDI\t%2,R0\;BRA\t%0"
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
+;
|
+;
|
+; and for
|
+; and for
|
+; BRA target
|
+; BRA target
|
+; BRA target ; two branches to the same identical target in a row ...
|
+; BRA target ; two branches to the same identical target in a row ...
|
+;
|
+;
|
| Line 9268... |
Line 9926... |
+// change needed to be made in machmodes.def. Hence, here is a target
|
+// change needed to be made in machmodes.def. Hence, here is a target
|
+// configuration change--in machmodes.def--that properly belonged in the
|
+// configuration change--in machmodes.def--that properly belonged in the
|
+// config directory.
|
+// config directory.
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
|
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-04-06 14:25:35.431154171 -0400
|
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-04-21 16:19:02.122215475 -0400
|
@@ -0,0 +1,78 @@
|
@@ -0,0 +1,82 @@
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+//
|
+//
|
+// Filename: zip-protos.h
|
+// Filename: zip-protos.h
|
+//
|
+//
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
| Line 9308... |
Line 9966... |
+//
|
+//
|
+////////////////////////////////////////////////////////////////////////////////
|
+////////////////////////////////////////////////////////////////////////////////
|
+#ifndef ZIP_PROTOS_H
|
+#ifndef ZIP_PROTOS_H
|
+#define ZIP_PROTOS_H
|
+#define ZIP_PROTOS_H
|
+
|
+
|
|
+extern bool zip_supported_condition(int c);
|
+extern void zip_expand_prologue(void);
|
+extern void zip_expand_prologue(void);
|
+extern void zip_expand_epilogue(void);
|
+extern void zip_expand_epilogue(void);
|
|
+extern void zip_expand_movsicc(rtx,rtx,rtx,rtx);
|
+extern int zip_initial_elimination_offset(int, int);
|
+extern int zip_initial_elimination_offset(int, int);
|
+extern void zip_print_operand(FILE *, rtx, int);
|
+extern void zip_print_operand(FILE *, rtx, int);
|
+extern void zip_print_operand_address(FILE *, rtx);
|
+extern void zip_print_operand_address(FILE *, rtx);
|
+extern enum reg_class zip_reg_class(int);
|
+extern enum reg_class zip_reg_class(int);
|
+extern rtx zip_return_addr_rtx(int, rtx);
|
+extern rtx zip_return_addr_rtx(int, rtx);
|
| Line 9331... |
Line 9991... |
+extern bool zip_gen_move_rtl(rtx, rtx);
|
+extern bool zip_gen_move_rtl(rtx, rtx);
|
+extern bool zip_use_return_insn(void);
|
+extern bool zip_use_return_insn(void);
|
+extern const char *zip_set_zero_or_one(rtx, rtx);
|
+extern const char *zip_set_zero_or_one(rtx, rtx);
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
+
|
+
|
|
+extern int zip_insn_sets_cc(rtx_insn *insn);
|
|
+extern int zip_is_conditional(rtx_insn *insn);
|
+extern int zip_ct_address_operand(rtx op);
|
+extern int zip_ct_address_operand(rtx op);
|
+extern int zip_pd_opb_operand(rtx op);
|
+extern int zip_pd_opb_operand(rtx op);
|
+extern int zip_pd_mov_operand(rtx op);
|
+extern int zip_pd_mov_operand(rtx op);
|
+extern int zip_pd_imm_operand(rtx op);
|
+extern int zip_pd_imm_operand(rtx op);
|
+extern int zip_pd_mvimm_operand(rtx op);
|
+extern int zip_pd_mvimm_operand(rtx op);
|
| Line 9501... |
Line 10163... |
+#elif BITS_PER_UNIT == 32
|
+#elif BITS_PER_UNIT == 32
|
+#define LOG2_BITS_PER_UNIT 5
|
+#define LOG2_BITS_PER_UNIT 5
|
#else
|
#else
|
#error Unknown BITS_PER_UNIT
|
#error Unknown BITS_PER_UNIT
|
#endif
|
#endif
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c
|
|
--- gcc-5.3.0-original/gcc/df-scan.c 2015-01-09 15:18:42.000000000 -0500
|
|
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400
|
|
@@ -61,6 +61,14 @@
|
|
|
|
typedef struct df_mw_hardreg *df_mw_hardreg_ptr;
|
|
|
|
+// #define DO_ZIP_DEBUGS
|
|
+#ifdef DO_ZIP_DEBUGS
|
|
+extern void zip_debug_rtx(const_rtx);
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
|
+#else
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
|
+#endif
|
|
+
|
|
|
|
#ifndef HAVE_epilogue
|
|
#define HAVE_epilogue 0
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
|
--- gcc-5.3.0-original/gcc/doc/gcc.log 1969-12-31 19:00:00.000000000 -0500
|
--- gcc-5.3.0-original/gcc/doc/gcc.log 1969-12-31 19:00:00.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/doc/gcc.log 2016-01-30 15:18:43.262724969 -0500
|
+++ gcc-5.3.0-zip/gcc/doc/gcc.log 2016-01-30 15:18:43.262724969 -0500
|
@@ -0,0 +1,214 @@
|
@@ -0,0 +1,214 @@
|
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7) 30 JAN 2016 15:17
|
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7) 30 JAN 2016 15:17
|
| Line 9721... |
Line 10401... |
+
|
+
|
+./include/gcc-common.texi:11: ==> Fatal error occurred, no output PDF file pro
|
+./include/gcc-common.texi:11: ==> Fatal error occurred, no output PDF file pro
|
+duced!
|
+duced!
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
|
--- gcc-5.3.0-original/gcc/emit-rtl.c 2015-08-05 07:20:59.000000000 -0400
|
--- gcc-5.3.0-original/gcc/emit-rtl.c 2015-08-05 07:20:59.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-04-01 06:40:42.812171791 -0400
|
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-04-20 20:54:45.148982373 -0400
|
@@ -81,6 +81,15 @@
|
@@ -81,6 +81,15 @@
|
#include "builtins.h"
|
#include "builtins.h"
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
| Line 9738... |
Line 10418... |
+#endif
|
+#endif
|
+
|
+
|
struct target_rtl default_target_rtl;
|
struct target_rtl default_target_rtl;
|
#if SWITCHABLE_TARGET
|
#if SWITCHABLE_TARGET
|
struct target_rtl *this_target_rtl = &default_target_rtl;
|
struct target_rtl *this_target_rtl = &default_target_rtl;
|
@@ -2925,6 +2934,8 @@
|
@@ -2979,6 +2988,8 @@
|
int copied = 0;
|
|
int length;
|
|
|
|
+ZIP_DEBUG_LINE("Copy RTX if shared",*orig1);
|
|
+
|
|
/* Repeat is used to turn tail-recursion into iteration. */
|
|
repeat:
|
|
x = *orig1;
|
|
@@ -2979,6 +2990,8 @@
|
|
break;
|
break;
|
}
|
}
|
|
|
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
|
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
|
+
|
+
|
/* This rtx may not be shared. If it has already been seen,
|
/* This rtx may not be shared. If it has already been seen,
|
replace it with a copy of itself. */
|
replace it with a copy of itself. */
|
|
|
@@ -2989,6 +3002,8 @@
|
@@ -2989,6 +3000,8 @@
|
}
|
}
|
RTX_FLAG (x, used) = 1;
|
RTX_FLAG (x, used) = 1;
|
|
|
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
|
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
|
+
|
+
|
/* Now scan the subexpressions recursively.
|
/* Now scan the subexpressions recursively.
|
We can store any replaced subexpressions directly into X
|
We can store any replaced subexpressions directly into X
|
since we know X is not shared! Any vectors in X
|
since we know X is not shared! Any vectors in X
|
|
@@ -3665,7 +3678,9 @@
|
|
split_branch_probability = XINT (note, 0);
|
|
probability = split_branch_probability;
|
|
|
|
+ZIP_DEBUG_LINE("Before split", trial);
|
|
seq = safe_as_a <rtx_insn *> (split_insns (pat, trial));
|
|
+ZIP_DEBUG_LINE("After split", seq);
|
|
|
|
split_branch_probability = -1;
|
|
|
|
@@ -3834,6 +3849,7 @@
|
|
if (! tem->deleted () && INSN_P (tem))
|
|
tem = try_split (PATTERN (tem), tem, 1);
|
|
|
|
+
|
|
/* Return either the first or the last insn, depending on which was
|
|
requested. */
|
|
return last
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
|
--- gcc-5.3.0-original/gcc/expr.c 2015-04-07 10:34:06.000000000 -0400
|
--- gcc-5.3.0-original/gcc/expr.c 2015-04-07 10:34:06.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/expr.c 2016-03-08 04:07:01.426335724 -0500
|
+++ gcc-5.3.0-zip/gcc/expr.c 2016-03-08 04:07:01.426335724 -0500
|
@@ -7999,6 +7999,8 @@
|
@@ -7999,6 +7999,8 @@
|
the back of the caller.
|
the back of the caller.
|
| Line 9779... |
Line 10468... |
rtx
|
rtx
|
expand_expr_real (tree exp, rtx target, machine_mode tmode,
|
expand_expr_real (tree exp, rtx target, machine_mode tmode,
|
enum expand_modifier modifier, rtx *alt_rtl,
|
enum expand_modifier modifier, rtx *alt_rtl,
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
|
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500
|
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-12 22:11:51.147370235 -0400
|
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-20 20:52:07.186056061 -0400
|
@@ -109,6 +109,14 @@
|
@@ -109,6 +109,14 @@
|
#include "wide-int-print.h"
|
#include "wide-int-print.h"
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
| Line 10165... |
Line 10854... |
return apply_change_group ();
|
return apply_change_group ();
|
}
|
}
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
|
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400
|
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400
|
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-06 17:45:29.552304498 -0400
|
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-14 23:19:07.630839483 -0400
|
@@ -68,6 +68,15 @@
|
@@ -68,6 +68,15 @@
|
#include "df.h"
|
#include "df.h"
|
#include "insn-codes.h"
|
#include "insn-codes.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
| Line 10208... |
Line 10897... |
}
|
}
|
#endif /* HAVE_peephole2 */
|
#endif /* HAVE_peephole2 */
|
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
|
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500
|
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500
|
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-13 11:32:23.013097569 -0400
|
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-20 20:51:38.590252867 -0400
|
@@ -72,6 +72,14 @@
|
@@ -72,6 +72,14 @@
|
#include "dumpfile.h"
|
#include "dumpfile.h"
|
#include "rtl-iter.h"
|
#include "rtl-iter.h"
|
|
|
+// #define DO_ZIP_DEBUGS
|
+// #define DO_ZIP_DEBUGS
|
| Line 10224... |
Line 10913... |
+#endif
|
+#endif
|
+
|
+
|
/* This file contains the reload pass of the compiler, which is
|
/* This file contains the reload pass of the compiler, which is
|
run after register allocation has been done. It checks that
|
run after register allocation has been done. It checks that
|
each insn is valid (operands required to be in registers really
|
each insn is valid (operands required to be in registers really
|
@@ -794,6 +802,18 @@
|
@@ -794,6 +802,20 @@
|
basic_block bb;
|
basic_block bb;
|
bool inserted;
|
bool inserted;
|
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+ {
|
+ {
|
|
+ fprintf(stderr, "BEFORE-RELOAD\n");
|
+ int total_count = 0, current_count = 0;
|
+ int total_count = 0, current_count = 0;
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
+ total_count++;
|
+ total_count++;
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
+ fprintf(stderr, "B %3d/%3d", current_count++, total_count);
|
+ fprintf(stderr, "B %3d/%3d", current_count++, total_count);
|
+ zip_debug_rtx(insn);
|
+ zip_debug_rtx(insn);
|
+ }
|
+ }
|
|
+ fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n");
|
+ }
|
+ }
|
+#endif
|
+#endif
|
+
|
+
|
/* Make sure even insns with volatile mem refs are recognizable. */
|
/* Make sure even insns with volatile mem refs are recognizable. */
|
init_recog ();
|
init_recog ();
|
|
|
@@ -1366,6 +1386,18 @@
|
@@ -1366,6 +1388,20 @@
|
|
|
reload_completed = !failure;
|
reload_completed = !failure;
|
|
|
+#ifdef DO_ZIP_DEBUGS
|
+#ifdef DO_ZIP_DEBUGS
|
+ {
|
+ {
|
|
+ fprintf(stderr, "AFTER-RELOAD\n");
|
+ int total_count = 0, current_count = 0;
|
+ int total_count = 0, current_count = 0;
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
+ total_count++;
|
+ total_count++;
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
+ fprintf(stderr, "A %3d/%3d", current_count++, total_count);
|
+ fprintf(stderr, "A %3d/%3d", current_count++, total_count);
|
+ zip_debug_rtx(insn);
|
+ zip_debug_rtx(insn);
|
+ }
|
+ }
|
|
+ fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n");
|
+ }
|
+ }
|
+#endif
|
+#endif
|
+
|
+
|
return need_dce;
|
return need_dce;
|
}
|
}
|
