OpenCores

Rev 202	Rev 209
Line 160...	Line 160...
`esac`	`esac`

`# If we aren't building newlib, then don't build libgloss, since libgloss`	`# If we aren't building newlib, then don't build libgloss, since libgloss`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c`
`--- gcc-6.2.0/gcc/cfgexpand.c 2016-04-27 08:23:50.000000000 -0400`	`--- gcc-6.2.0/gcc/cfgexpand.c 2016-04-27 08:23:50.000000000 -0400`
`+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2016-12-31 16:38:36.195534819 -0500`	`+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2018-06-05 21:18:19.438798488 -0400`
`@@ -74,6 +74,15 @@`	`@@ -74,6 +74,16 @@`
`#include "tree-chkp.h"`	`#include "tree-chkp.h"`
`#include "rtl-chkp.h"`	`#include "rtl-chkp.h"`

`+`	`+`
	`+// #define DO_ZIP_DEBUGS`
`+#ifdef DO_ZIP_DEBUGS`	`+#ifdef DO_ZIP_DEBUGS`
`+#include <stdio.h>`	`+#include <stdio.h>`
`+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)`	`+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)`
`+extern void zip_debug_rtx(const_rtx);`	`+extern void zip_debug_rtx(const_rtx);`
`+#else`	`+#else`
Line 177...	Line 178...
`+#endif`	`+#endif`
`+`	`+`
`/* Some systems use __main in a way incompatible with its use in gcc, in these`	`/* Some systems use __main in a way incompatible with its use in gcc, in these`
`cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to`	`cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to`
`give the same symbol without quotes for an alternative entry point. You`	`give the same symbol without quotes for an alternative entry point. You`
`@@ -1172,7 +1181,7 @@`	`@@ -1172,7 +1182,7 @@`
`base_align = crtl->max_used_stack_slot_alignment;`	`base_align = crtl->max_used_stack_slot_alignment;`
`else`	`else`
`base_align = MAX (crtl->max_used_stack_slot_alignment,`	`base_align = MAX (crtl->max_used_stack_slot_alignment,`
`- GET_MODE_ALIGNMENT (SImode)`	`- GET_MODE_ALIGNMENT (SImode)`
`+ GET_MODE_ALIGNMENT (word_mode)`	`+ GET_MODE_ALIGNMENT (word_mode)`
`<< ASAN_SHADOW_SHIFT);`	`<< ASAN_SHADOW_SHIFT);`
`}`	`}`
`else`	`else`
`@@ -2225,7 +2234,7 @@`	`@@ -2225,7 +2235,7 @@`
`data.asan_vec.safe_push (offset);`	`data.asan_vec.safe_push (offset);`
`/* Leave space for alignment if STRICT_ALIGNMENT. */`	`/* Leave space for alignment if STRICT_ALIGNMENT. */`
`if (STRICT_ALIGNMENT)`	`if (STRICT_ALIGNMENT)`
`- alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)`	`- alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)`
`+ alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)`	`+ alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)`
`<< ASAN_SHADOW_SHIFT)`	`<< ASAN_SHADOW_SHIFT)`
`/ BITS_PER_UNIT, 1);`	`/ BITS_PER_UNIT, 1);`

`@@ -5745,7 +5754,7 @@`	`@@ -5745,7 +5755,7 @@`
`&& (last = get_last_insn ())`	`&& (last = get_last_insn ())`
`&& JUMP_P (last))`	`&& JUMP_P (last))`
`{`	`{`
`- rtx dummy = gen_reg_rtx (SImode);`	`- rtx dummy = gen_reg_rtx (SImode);`
`+ rtx dummy = gen_reg_rtx (word_mode);`	`+ rtx dummy = gen_reg_rtx (word_mode);`
Line 298...	Line 299...
`+`	`+`
`+#undef TARGET_OPTION_OPTIMIZATION_TABLE`	`+#undef TARGET_OPTION_OPTIMIZATION_TABLE`
`+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table`	`+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table`
`+`	`+`
`+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;`	`+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;`
	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops gcc-6.2.0-zip/gcc/config/zip/genzipops`
	`--- gcc-6.2.0/gcc/config/zip/genzipops 1969-12-31 19:00:00.000000000 -0500`
	`+++ gcc-6.2.0-zip/gcc/config/zip/genzipops 2018-03-22 18:33:09.823726748 -0400`
	`@@ -0,0 +1,201 @@`
	+ELF>@@�N@8 @@@@@@��88@8@@@�9�9 >>`>`�� (>(>`(>`��TT@T@DDP�td�6�6@�6@��Q�tdR�td>>`>`��/lib64/ld-linux-x86-64.so.2GNU GNU��F3m��+�Z\L�=��<9�4B;#tm^� fWPI�@`libc.so.6exitsprintffopenputs__stack_chk_failunlinkstrlenfclosestderrfwriterenamefprintfaccessstrcmp__libc_start_main__gmon_start__GLIBC_2.4GLIBC_2.2.5ii �ui ��?` �@`@` @`(@`0@`8@`@@`H@`P@`X@`
	+`@`h@`p@` x@`�@`H��H�9 H��t�H��59 �%9 @�%9 h��%�8 h��%�8 h��%�8 h��%�8 h��%�8 h��%�8 h��%�8 h�p��%�8 h�`��%�8 h �P��%�8 h
	+�@��%�8 h�0��%�8 h� ��%�8 h ��%8 f�1�I��^H��H��PTI��@H��@H��>@�7��fD��@`UH-�@`H��H��v�H��t]��@`��f�]�@f.��@`UH��@`H��H��H��H��?H�H��t�H��t]��@`��]�fD�=8 uUH��n��]��7 ��@� >`H�?u��H��t�UH��]�z��UH��H��H�}�H�E�H��@��UH��H��H�}�H�u�H�U�H�E�� @H�Ǹ�6��UH��H��0H�}�H�u�H�U�H�M�L�E�L�M�H�}�H�u�H�M�H�U�H�E�H��u�u��u�I��I�� @H�Ǹ��H�� UH��H��H��h��H��`��H��X��H��P��L��H��L��@��H�EH��8��dH�%(H�E�1�H��8��H��p��!@H�Ǹ��H��8��H��h��!@H�Ǹ�D��H��8��H��P��H��X��H��`��H��h��H��`��I��I��!@H�Ǹ��H��H��8��H��P��H��@��H��`��H��h��H��`��I��I��"@H�Ǹ��H��H��8��H��P��H��@��H��`��H��h��H��h?#@A�<#@I��H��B��H��H��8��H��P��H��@��H��`��H��h��H��hD#@A�A#@I��H��H��H��8��H��P��H��@��H��`��H��h��H��hJ#@A�G#@I��H��H��H��8��H��P��H��@��H��`��H��h��H��hP#@A�M#@I��H��H��H��8��H��P��H��@��H��`��H��h��H��hW#@A�S#@I��H��>��H��H��8��H��P��H��@��H��`��H��h��H��h]#@A�Y#@I��H��H��H�E�dH3%(t��UH��H��H��H��H��H��L��dH�%(H�E�1�H��H��`#@H�Ǹ��H��H��$@H�Ǹ��H��H��8$@H�Ǹ��L��H��H��H��H��H��H��M��I��H��c��H��H��H��$@H�Ǹ�R��H��H��%@H�Ǹ�2��H��H��%@H�Ǹ��H��H��&@H�Ǹ��L��H��H��H��H��H��H��M��I��H��H��H�E�dH3%(t�'��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�H��u��u��u�I��I��&@H�Ǹ��H�� UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��(@H�Ǹ��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��`)@H�Ǹ�r��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��*@H�Ǹ�+��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��+@H�Ǹ��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��,@H�Ǹ��UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��(.@H�Ǹ�V��UH��p/@��]�UH��AUATSH��(�}�H�u�H�?0 ��/@H��:��H�E�H�/0 H�EЃ}�~!H�E�H��H��<-u��4��}��H�E�H��H�H��H��H��/ H��u��H9�r~H��/ H�E�H��L� H�E�H��H�H��K��I��H��/ H��9��I)�L��L�H��H��U��u/H�E�H��H��H��Y��uH�E�H��H�H��H�E�H�@H�E�H�E�H��H�E�A��/@��/@��/@��/@H��H�E�A��/@��/@��/@��/@H��H�E�A��/@��/@��/@��/@H��H�E�A��/@��/@�0@�0@H��H�E�A�0@��/@�0@�0@H��`��H�E�A�$0@��/@�(0@�/0@H��?��H�E�A�60@��/@�90@�@0@H��H�E�A�G0@��/@�K0@�R0@H��H�E�A�Y0@��/@�]0@�i0@H��H�E�A�q0@��/@�u0@�0@H��H�E�A��0@��/@��0@��0@H��H�E�H��h3@A��0@A�x1@�
	`+2@�2@�3@H��H��H�E�H��h�5@A� 3@A��3@�`
	+2@��4@�5@H��x��H��H�Eؾ�5@H��H�Eع?#@�<#@��5@H��H�EعD#@�A#@��5@H��H�EعJ#@�G#@��5@H��H�EعP#@�M#@��5@H��u��H�EعW#@�S#@��5@H��Z��H�Eع]#@�Y#@��5@H��?��H�Eؾ�5@H��#��H�Eع?#@�<#@��5@H��k��H�EعD#@�A#@��5@H��P��H�EعJ#@�G#@��5@H��5��H�EعP#@�M#@��5@H��H�EعW#@�S#@��5@H��H�Eع]#@�Y#@��5@H��H�Eؾ�5@H��p��H�Eع?#@�<#@�6@H��F��H�EعD#@�A#@�6@H��+��H�EعJ#@�G#@�6@H��H�EعP#@�M#@�6@H��H�EعW#@�S#@�6@H��H�Eع]#@�Y#@�6@H��H�Eؾ6@H��H�Eع?#@�<#@�"6@H��L��H�EعD#@�A#@�"6@H��1��H�EعJ#@�G#@�"6@H��H�EعP#@�M#@�"6@H��H�EعW#@�S#@�"6@H��H�Eع]#@�Y#@�"6@H��H�Eؾ'6@H��
	+��H�Eع?#@�<#@�D6@H��'��H�EعD#@�A#@�D6@H��H�EعJ#@�G#@�D6@H��H�EعP#@�M#@�D6@H��H�EعW#@�S#@�D6@H��H�Eع]#@�Y#@�D6@H��H�EؾI6@H��W��H�Eع?#@�<#@�f6@H��H�EعD#@�A#@�f6@H��H�EعJ#@�G#@�f6@H��H�EعP#@�M#@�f6@H��j��H�EعW#@�S#@�f6@H��O��H�Eع]#@�Y#@�f6@H��4��H�Eؾk6@H��H�Eع?#@�<#@��6@H��O��H�EعD#@�A#@��6@H��4��H�EعJ#@�G#@��6@H��H�EعP#@�M#@��6@H��H�EعW#@�S#@��6@H��H�Eع]#@�Y#@��6@H��H�E�H��H�g( H�U�H��H��p��t.H� M( H�n( H�Uо�6@H�Ǹ��^��T��@AWAVA��AUATL�%~% UH�-~% SI��I��L)�H��H��'��H��t 1��L��L��D��A��H��H9�u�H��[]A\A]A^A_Ðf.��H��H��;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	`+;;`
	`+;; Filename: zip-ops.md`
	`+;;`
	`+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
	`+;;`
	`+;; Purpose: This is a computer generated machine description of the`
	`+;; ZipCPU's operations. It is computer generated simply for`
	`+;; two reasons. First, I can't seem to find a way to generate this`
	`+;; information within GCC's current constructs. Specifically, the`
	`+;; CPU's instructions normally set the condition codes, unless they`
	`+;; are conditional instructions when they don't. Second, the ZipCPU is`
	`+;; actually quite regular. Almost all of the instructions have the same`
	`+;; form. This form turns into many, many RTL instructions. Because the`
	`+;; CPU doesn't match any of the others within GCC, that means either`
	`+;; I have a lot of cut, copy, paste, and edit to do to create the file`
	`+;; and upon any and every edit, or I need to build a program to generate`
	`+;; the remaining .md constructs. Hence, I chose the latter to minimize`
	`+;; the amount of work I needed to do.`
	`+;;`
	`+;;`
	`+;; Creator: Dan Gisselquist, Ph.D.`
	`+;; Gisselquist Technology, LLC`
	`+;;`
	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
	`+;;`
	`+;; Copyright (C) 2017, Gisselquist Technology, LLC`
	`+;;`
	`+;; This program is free software (firmware): you can redistribute it and/or`
	`+;; modify it under the terms of the GNU General Public License as published`
	`+;; by the Free Software Foundation, either version 3 of the License, or (at`
	`+;; your option) any later version.`
	`+;;`
	`+;; This program is distributed in the hope that it will be useful, but WITHOUT`
	`+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
	`+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
	`+;; for more details.`
	`+;;`
	`+;; License: GPL, v3, as defined and found on www.gnu.org,`
	`+;; http://www.gnu.org/licenses/gpl.html`
	`+;;`
	`+;;`
	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
	`+;;`
	`+;;`
	`+;`
	`+;`
	`+; %s`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(cond_exec (%s (reg:CC CC_REG) (const_int 0))`
	`+ %s)]`
	`+ "%s" ; Condition`
	`+ "%s.%s\t%%1,%%0 ; genzip, conditional operator" ; Template`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+%s (genzipop_long);`
	`+;`
	`+;`
	`+; %s (genzipop_long)`
	`+;`
	`+;`
	`+;`
	`+(define_insn "%s"`
	`+ [%s`
	`+ (clobber (reg:CC CC_REG))]`
	`+ "%s"`
	`+ "%s\t%%2,%%0 ; %s"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])`
	`+;`
	`+;`
	`+(define_insn "%s_raw"`
	`+ [%s`
	`+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]`
	`+ "%s"`
	`+ "%s\t%%1,%%0 ; %s_raw"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])`
	`+;`
	`+;`
	`+eqZneNZltLTgeGEltuCgeuNC(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (%s (match_operand:SI 1 "register_operand" "0")`
	`+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (%s (match_dup 0)`
	`+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (%s (match_operand:SI 1 "register_operand" "0")`
	`+ (plus:SI (match_operand:SI 2 "register_operand" "r")`
	`+ (match_operand:SI 3 "const_int_operand" "N"))))(set (match_dup 0) (%s (match_dup 0)`
	`+ (plus:SI (match_dup 2) (match_dup 3))))(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (%s (match_dup 0)`
	`+ (plus:SI (match_operand:SI 1 "register_operand" "r")`
	`+ (match_operand:SI 2 "const_int_operand" "N"))))%s_off;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (match_operand:SI 1 "general_operand" "r,Q,i,r")`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "@`
	`+ MOV.%s %%1,%%0 ; cmov`
	`+ LW.%s %%1,%%0 ; cmov`
	`+ LDI.%s %%1,%%0 ; cmov`
	`+ SW.%s %%1,%%0 ; cmov"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (plus:SI (match_dup 0)`
	`+ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "ADD.%s %%1,%%0 ; cadd"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (xor:SI (match_dup 0)`
	`+ (const_int -1))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "NOT.%s %%0 ; cnot"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "+r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (neg:SI (match_dup 0))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "NEG.%s %%0 ; cneg"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "+r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "AND.%s %%1,%%0 ; cand"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "+r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "OR.%s %%1,%%0 ; cior"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+;`
	`+;`
	`+(define_insn "%s_%s"`
	`+ [(set (match_operand:SI 0 "register_operand" "+r")`
	`+ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))`
	`+ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))`
	`+ (match_dup 0)))]`
	`+ ""`
	`+ "XOR.%s %%1,%%0 ; cxor"`
	`+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])`
	`+USAGE: genzipops <new-zip-ops.md filename>.zip-ops.mdzip-ops.mdwADDplus:SIaddsi3SUBminus:SIsubsi3MPYmult:SImulsi3DIVS(ZIP_DIVIDE)div:SIdivsi3DIVUudiv:SIudivsi3ANDand:SIandsi3ORior:SIiorsi3XORxor:SIxorsi3ASRashiftrt:SIashrsi3LSLashift:SIashlsi3LSRlshiftrt:SIlshrsi3(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (sign_extend:DI (match_dup 0))`
	`+ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))`
	`+ (const_int 32))))(set (match_dup 0)`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (sign_extend:DI (match_dup 1))`
	`+ (sign_extend:DI (match_dup 2)))`
	`+ (const_int 32))))(ZIP_HAS_DI)(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))`
	`+ (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))`
	`+ (const_int 32))))smulsi_highpartMPYSHI(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (zero_extend:DI (match_dup 0))`
	`+ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))`
	`+ (const_int 32))))(set (match_dup 0)`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (zero_extend:DI (match_dup 1))`
	`+ (zero_extend:DI (match_dup 2)))`
	`+ (const_int 32))))(set (match_operand:SI 0 "register_operand" "=r")`
	`+ (truncate:SI (ashiftrt:DI (mult:DI`
	`+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))`
	`+ (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))`
	`+ (const_int 32))))umulsi_highpartMPYUHIConditional move instructionscmovConditional add instructionscaddConditional negate instructionscnegConditional not instructionscnotConditional and instructionscandConditional ior instructionsciorConditional xor instructionscxorERR: Could not create %s, leaving results in %s`
	+;�<��<��2��\��,��L��l��g��M��,��L"��li��z��,��zRx��zRx�$P��FJw�?;3$"D��*A�C ed(��-A�C h�5��`A�C [�u��A�C ��A�C ��XA�C S��GA�C B$��GA�C BD9��GA�C Bd`��GA�C B��GA�C B��GA�C B��A�C L��>A�C I��D��eB�B�E �B(�H0�H8�M@r8A0A(B BBBL��@�@�@ �@>`>`��o�@X@�@
	+�@`P�@X@0 ��o(@��o��o@(>`@&@6@F@V@f@v@�@�@�@�@�@�@�@�/@�/@GCC: (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 201606098@T@t@�@�@X@@(@ X@
	+�@�@@ �@@�@@�6@`7@>`>` >`(>`�?`@`�@`�@`�� >`0@p@.�@D�@`S>`z�@�>`��9@� >`��>`�(>`�>`��6@@`!�@1�@G9M - �@`i+@Xq��@`�k@��M @`��@`��@`�+�@�� @��@G+�@`8LX@GTi x�@`�@��@e��@`� @-1@��@G��@G��@`�>@>�-@�� &�@,ASg�@`s �@G��@��@`crtstuff.c__JCR_LIST__deregister_tm_clones__do_global_dtors_auxcompleted.7594__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entrygenzipops.c__FRAME_END____JCR_END____init_array_end_DYNAMIC__init_array_start__GNU_EH_FRAME_HDR_GLOBAL_OFFSET_TABLE___libc_csu_finigenciorunlink@@GLIBC_2.2.5_ITM_deregisterTMCloneTablegencmovputs@@GLIBC_2.2.5TAILPATHgenzipopgenzip_condopTMPPATH_edatafclose@@GLIBC_2.2.5strlen@@GLIBC_2.2.5__stack_chk_fail@@GLIBC_2.4genzipop_longgencnot__libc_start_main@@GLIBC_2.2.5__data_startstrcmp@@GLIBC_2.2.5gencandfprintf@@GLIBC_2.2.5__gmon_start____dso_handle_IO_stdin_used__libc_csu_initgen_headinggencxorgencadd__bss_startmainusageaccess@@GLIBC_2.2.5fopen@@GLIBC_2.2.5_Jv_RegisterClassesrename@@GLIBC_2.2.5legalsprintf@@GLIBC_2.2.5exit@@GLIBC_2.2.5fwrite@@GLIBC_2.2.5__TMC_END___ITM_registerTMCloneTablegencnegstderr@@GLIBC_2.2.5.symtab.strtab.shstrtab.interp.note.ABI-tag.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.got.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.jcr.dynamic.got.plt.data.bss.comment8@8#T@T 1t@t$D��o�@�$N�@��VX@X�^��o@"k��o(@(0zX@X0�B�@�P��@��@��@��@��@� �@��6@�6��`7@`7��>`>�>`>� >` >�(>`(>��?`�?�@`@��@`�@ ��@`�@ 0�@4qM�@�/ �I�
	`\ No newline at end of file`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c`
`--- gcc-6.2.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500`	`--- gcc-6.2.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500`
`+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c 2017-03-07 12:03:59.062584503 -0500`	`+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c 2017-03-07 12:03:59.062584503 -0500`
`@@ -0,0 +1,444 @@`	`@@ -0,0 +1,444 @@`
`+////////////////////////////////////////////////////////////////////////////////`	`+////////////////////////////////////////////////////////////////////////////////`
Line 748...	Line 955...
`+ exit(EXIT_FAILURE);`	`+ exit(EXIT_FAILURE);`
`+ } exit(EXIT_SUCCESS);`	`+ } exit(EXIT_SUCCESS);`
`+}`	`+}`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c`
`--- gcc-6.2.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500`	`--- gcc-6.2.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500`
`+++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2017-03-07 12:03:18.566583672 -0500`	`+++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2018-06-05 21:17:24.151098201 -0400`
`@@ -0,0 +1,2679 @@`	`@@ -0,0 +1,2711 @@`
`+////////////////////////////////////////////////////////////////////////////////`	`+////////////////////////////////////////////////////////////////////////////////`
`+//`	`+//`
`+// Filename: zip.c`	`+// Filename: zip.c`
`+//`	`+//`
`+// Project: Zip CPU backend for the GNU Compiler Collection`	`+// Project: Zip CPU backend for the GNU Compiler Collection`
Line 2500...	Line 2707...
`+ strcpy(mstr, ":QI");`	`+ strcpy(mstr, ":QI");`
`+ else if (GET_MODE(x) == HImode)`	`+ else if (GET_MODE(x) == HImode)`
`+ strcpy(mstr, ":HI");`	`+ strcpy(mstr, ":HI");`
`+ else if (GET_MODE(x) == SImode)`	`+ else if (GET_MODE(x) == SImode)`
`+ strcpy(mstr, ":SI");`	`+ strcpy(mstr, ":SI");`
	`+ else if (GET_MODE(x) == DImode)`
	`+ strcpy(mstr, ":DI");`
	`+ else if (GET_MODE(x) == SFmode)`
	`+ strcpy(mstr, ":SF");`
	`+ else if (GET_MODE(x) == DFmode)`
	`+ strcpy(mstr, ":DF");`
`+ else if (GET_MODE(x) == VOIDmode)`	`+ else if (GET_MODE(x) == VOIDmode)`
`+ strcpy(mstr, ":V");`	`+ strcpy(mstr, ":V");`
`+ else`	`+ else`
`+ strcpy(mstr, ":?");`	`+ strcpy(mstr, ":?");`
`+ if (REG_P(XEXP(x,0))) {`	`+ if (REG_P(XEXP(x,0))) {`
`+ int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),`	`+ int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),`
`+ sb = SUBREG_BYTE(x);`	`+ sb = SUBREG_BYTE(x);`
`+ if (mod==QImode)`	`+ if (mod==SFmode)`
`+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);`	`+ sprintf(buf,"(SUBREG%s (REG:SF %d)/%d)",mstr,hreg, sb);`
	`+ else if (mod==DFmode)`
	`+ sprintf(buf,"(SUBREG%s (REG:DF %d)/%d)",mstr,hreg, sb);`
	`+ else if (mod==DImode)`
	`+ sprintf(buf,"(SUBREG%s (REG:DI %d)/%d)",mstr,hreg, sb);`
	`+ else if (mod==SImode)`
	`+ sprintf(buf,"(SUBREG%s (REG:SI %d)/%d)",mstr,hreg, sb);`
`+ else if (mod==HImode)`	`+ else if (mod==HImode)`
`+ sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);`	`+ sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);`
`+ else if (mod==QImode)`	`+ else if (mod==QImode)`
`+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);`	`+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);`
`+ else if (mod==VOIDmode)`	`+ else if (mod==VOIDmode)`
Line 2944...	Line 3163...
`+`	`+`
`+ emit_insn(gen_movdi_raw(dst, src));`	`+ emit_insn(gen_movdi_raw(dst, src));`
`+ return 1;`	`+ return 1;`
`+ }`	`+ }`
`+`	`+`
	`+ // MOV SUBREG->REG`
	`+ if ((REG_P(dst))&&(SUBREG_P(src))) {`
	`+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- SUBREG->REG\n");`
	`+`
	`+ if (GET_MODE(src)==DImode) {`
	`+ emit_insn(gen_movdi_raw(dst, src));`
	`+ return 1;`
	`+ }`
	`+ }`
	`+`
	`+ // MOV REG->SUBREG`
	`+ if ((SUBREG_P(dst))&&(REG_P(src))) {`
	`+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->SUBREG\n");`
	`+`
	`+ if (GET_MODE(dst)==DImode) {`
	`+ emit_insn(gen_movdi_raw(dst, src));`
	`+ return 1;`
	`+ }`
	`+ }`
	`+`
`+ // MOV REG->MEM (a store instruction)`	`+ // MOV REG->MEM (a store instruction)`
`+ if ((MEM_P(dst))&&(REG_P(src))) {`	`+ if ((MEM_P(dst))&&(REG_P(src))) {`
`+ rtx addr = XEXP(dst,0);`	`+ rtx addr = XEXP(dst,0);`
`+ long offset = 0;`	`+ long offset = 0;`
`+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))`	`+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))`
Line 3443...	Line 3682...
`+#else`	`+#else`
`+#define ZIP_DEBUG_LINE(STR,RTX)`	`+#define ZIP_DEBUG_LINE(STR,RTX)`
`+#endif`	`+#endif`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md`
`--- gcc-6.2.0/gcc/config/zip/zip-di.md 1969-12-31 19:00:00.000000000 -0500`	`--- gcc-6.2.0/gcc/config/zip/zip-di.md 1969-12-31 19:00:00.000000000 -0500`
`+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2017-02-22 15:56:17.195319460 -0500`	`+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2018-06-05 18:57:29.386399718 -0400`
`@@ -0,0 +1,528 @@`	`@@ -0,0 +1,548 @@`
`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
`+;;`	`+;;`
`+;; Filename: zip-di.md`	`+;; Filename: zip-di.md`
`+;;`	`+;;`
`+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`	`+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
Line 3462...	Line 3701...
`+;; Creator: Dan Gisselquist, Ph.D.`	`+;; Creator: Dan Gisselquist, Ph.D.`
`+;; Gisselquist Technology, LLC`	`+;; Gisselquist Technology, LLC`
`+;;`	`+;;`
`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
`+;;`	`+;;`
`+;; Copyright (C) 2015, Gisselquist Technology, LLC`	`+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC`
`+;;`	`+;;`
`+;; This program is free software (firmware): you can redistribute it and/or`	`+;; This program is free software (firmware): you can redistribute it and/or`
`+;; modify it under the terms of the GNU General Public License as published`	`+;; modify it under the terms of the GNU General Public License as published`
`+;; by the Free Software Foundation, either version 3 of the License, or (at`	`+;; by the Free Software Foundation, either version 3 of the License, or (at`
`+;; your option) any later version.`	`+;; your option) any later version.`
Line 3506...	Line 3745...
`+ {`	`+ {`
`+ if ((REG_P(operands[0]))&&(REG_P(operands[1])))`	`+ if ((REG_P(operands[0]))&&(REG_P(operands[1])))`
`+ return "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";`	`+ return "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";`
`+ else if (MEM_P(operands[0])) //; StoreDI`	`+ else if (MEM_P(operands[0])) //; StoreDI`
`+ return "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";`	`+ return "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";`
`+ else if (MEM_P(operands[1])) //; LoadDI`	`+ else if (MEM_P(operands[1])) { //; LoadDI`
	`+ //; Deal with the case of`
	`+ //; LOD (R0),R0`
	`+ //; LOD 4(R0),R1`
	`+ //; By reversing the order of the operands, to`
	`+ //; LOD 4(R0),R1`
	`+ //; LOD (R0),R0`
	`+ //; This isn't efficient, so let's do whatever we can to`
	`+ //; avoid this, still ... if we do it, we can make it`
	`+ //; work`
	`+ rtx address = XEXP(operands[1],0);`
	`+ int hazard = 0;`
	`+ if ( (REG_P(address))`
	`+ &&((REGNO(address))==(REGNO(operands[0]))) )`
	`+ hazard = 1;`
	`+ else if ( (PLUS == (GET_CODE(address)))`
	`+ &&(REGNO(XEXP(address,0))==(REGNO(operands[0]))) )`
	`+ hazard = 1;`
	`+ if (hazard)`
	`+ return "LW 4+%1,%L0\t; Load:DI\n\tLW %1,%H0";`
	`+ else`
`+ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";`	`+ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";`
`+ else if (CONST_INT_P(operands[1])) {`	`+ } else if (CONST_INT_P(operands[1])) {`
`+ char tmp[128];`	`+ char tmp[128];`
`+ HOST_WIDE_INT v = INTVAL(operands[1]);`	`+ HOST_WIDE_INT v = INTVAL(operands[1]);`
`+ sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",`	`+ sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",`
`+ (unsigned)(v>>32),`	`+ (unsigned)(v>>32),`
`+ (unsigned)(v));`	`+ (unsigned)(v));`
Line 4117...	Line 4376...
`+;`	`+;`
`+;`	`+;`
`+;`	`+;`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h`
`--- gcc-6.2.0/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500`	`--- gcc-6.2.0/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500`
`+++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2017-03-03 09:30:57.671304970 -0500`	`+++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2018-06-05 22:22:38.581639662 -0400`
`@@ -0,0 +1,4114 @@`	`@@ -0,0 +1,4114 @@`
`+////////////////////////////////////////////////////////////////////////////////`	`+////////////////////////////////////////////////////////////////////////////////`
`+//`	`+//`
`+// Filename: gcc/config/zip/zip.h`	`+// Filename: gcc/config/zip/zip.h`
`+//`	`+//`
Line 4314...	Line 4573...
`+ * line. This constant is placed both before and after the value of LIB_SPEC.`	`+ * line. This constant is placed both before and after the value of LIB_SPEC.`
`+ *`	`+ *`
`+ * If this macro is not defined, the GCC driver provides a default that passes`	`+ * If this macro is not defined, the GCC driver provides a default that passes`
`+ * the string '-lgcc' to the linker.`	`+ * the string '-lgcc' to the linker.`
`+ */`	`+ */`
`+#undef LIBGCC_SPEC`	`+// #undef LIBGCC_SPEC`
`+#define LIBGCC_SPEC ""`	`+// #define LIBGCC_SPEC ""`
`+`	`+`
`+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the`	`+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the`
`+ * LIBGCC_SPEC is not directly used by the driver program but is instead`	`+ * LIBGCC_SPEC is not directly used by the driver program but is instead`
`+ * modified to refer to different versions of 'libgcc.a' depending on the`	`+ * modified to refer to different versions of 'libgcc.a' depending on the`
`+ * values of the command line flags '-static', '-shared', '-static-libgcc',`	`+ * values of the command line flags '-static', '-shared', '-static-libgcc',`
Line 4388...	Line 4647...
`+ * command line parameters we've been given indicate that our CPU has. That`	`+ * command line parameters we've been given indicate that our CPU has. That`
`+ * way, code can be adjusted depending upon the CPU's capabilities.`	`+ * way, code can be adjusted depending upon the CPU's capabilities.`
`+ */`	`+ */`
`+#define TARGET_CPU_CPP_BUILTINS() \`	`+#define TARGET_CPU_CPP_BUILTINS() \`
`+ { builtin_define("__ZIPCPU__"); \`	`+ { builtin_define("__ZIPCPU__"); \`
	`+ builtin_define("__BIG_ENDIAN__"); \`
`+ builtin_define("__IEEE_BIG_ENDIAN"); \`	`+ builtin_define("__IEEE_BIG_ENDIAN"); \`
`+ builtin_define("_LDBL_EQ_DBL"); \`	`+ builtin_define("_LDBL_EQ_DBL"); \`
`+ if (ZIP_FPU) builtin_define("__ZIPFPU__"); \`	`+ if (ZIP_FPU) builtin_define("__ZIPFPU__"); \`
`+ else builtin_define("_SOFT_FLOAT"); \`	`+ else builtin_define("_SOFT_FLOAT"); \`
`+ if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__"); \`	`+ if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__"); \`
Line 4440...	Line 4700...
`+ * ZipCPU floating point is barely going to be functional, I doubt it will`	`+ * ZipCPU floating point is barely going to be functional, I doubt it will`
`+ * support all of these bells and whistles when full functionality is even`	`+ * support all of these bells and whistles when full functionality is even`
`+ * achieved. Therefore, we won't support these modes. However, we can't just`	`+ * achieved. Therefore, we won't support these modes. However, we can't just`
`+ * set this to zero, so let's come back to this.`	`+ * set this to zero, so let's come back to this.`
`+ */`	`+ */`
`+// #warning "Wrong answer encoded to date"`
`+// #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P`	`+// #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P`
`+// #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0`	`+// #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0`
`+`	`+`
`+/* 17.04 Defining data structures for per-function information */`	`+/* 17.04 Defining data structures for per-function information */`
`+`	`+`
Line 7158...	Line 7417...
`+ * efficient.`	`+ * efficient.`
`+ */`	`+ */`
`+`	`+`
`+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive`	`+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive`
`+ * to specify the size of a symbol, without any arguments. ON systems that`	`+ * to specify the size of a symbol, without any arguments. ON systems that`
`+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to`	`+ * use ELF, the default is "\t.size\t"; on other systems, the default is not to`
`+ * define this macro.`	`+ * define this macro.`
`+ *`	`+ *`
`+ * Define this amcro only if it is correct to use the default definitions of`	`+ * Define this amcro only if it is correct to use the default definitions of`
`+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.`	`+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.`
`+ * If you need your own custom definitions of those macros, or if you do not`	`+ * If you need your own custom definitions of those macros, or if you do not`
Line 7214...	Line 7473...
`+ */`	`+ */`
`+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement`	`+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement`
`+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for`	`+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for`
`+ * claiming a register REGNO for a global variable DECL with name NAME.`	`+ * claiming a register REGNO for a global variable DECL with name NAME.`
`+ *`	`+ *`
`+ * If you don't defin this macro, that is equivalent to dfining it to do`	`+ * If you don't defin this macro, that is equivalent to defining it to do`
`+ * nothing.`	`+ * nothing.`
`+ */`	`+ */`
`+`	`+`
`+/* ASM_FINISH_DECLARE_OBJECT`	`+/* ASM_FINISH_DECLARE_OBJECT`
`+ * TARGET_ASM_GLOBALIZE_LABEL`	`+ * TARGET_ASM_GLOBALIZE_LABEL`
Line 8235...	Line 8494...
`+`	`+`
`+#endif /* GCC_ZIP_H */`	`+#endif /* GCC_ZIP_H */`
`+`	`+`
`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md`	`diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md`
`--- gcc-6.2.0/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500`	`--- gcc-6.2.0/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500`
`+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2017-03-07 12:02:29.862582673 -0500`	`+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2018-06-07 12:51:05.802342817 -0400`
`@@ -0,0 +1,1968 @@`	`@@ -0,0 +1,1897 @@`
`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
`+;;`	`+;;`
`+;; Filename: zip.md`	`+;; Filename: zip.md`
`+;;`	`+;;`
`+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`	`+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
Line 8252...	Line 8511...
`+;; Creator: Dan Gisselquist, Ph.D.`	`+;; Creator: Dan Gisselquist, Ph.D.`
`+;; Gisselquist Technology, LLC`	`+;; Gisselquist Technology, LLC`
`+;;`	`+;;`
`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`	`+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
`+;;`	`+;;`
`+;; Copyright (C) 2015-2017, Gisselquist Technology, LLC`	`+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC`
`+;;`	`+;;`
`+;; This program is free software (firmware): you can redistribute it and/or`	`+;; This program is free software (firmware): you can redistribute it and/or`
`+;; modify it under the terms of the GNU General Public License as published`	`+;; modify it under the terms of the GNU General Public License as published`
`+;; by the Free Software Foundation, either version 3 of the License, or (at`	`+;; by the Free Software Foundation, either version 3 of the License, or (at`
`+;; your option) any later version.`	`+;; your option) any later version.`
Line 8335...	Line 8594...
`+(define_constants`	`+(define_constants`

Line 160...

 esac

 esac

 # If we aren't building newlib, then don't build libgloss, since libgloss

 # If we aren't building newlib, then don't build libgloss, since libgloss

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c

--- gcc-6.2.0/gcc/cfgexpand.c   2016-04-27 08:23:50.000000000 -0400

--- gcc-6.2.0/gcc/cfgexpand.c   2016-04-27 08:23:50.000000000 -0400

+++ gcc-6.2.0-zip/gcc/cfgexpand.c       2016-12-31 16:38:36.195534819 -0500

+++ gcc-6.2.0-zip/gcc/cfgexpand.c       2018-06-05 21:18:19.438798488 -0400

@@ -74,6 +74,15 @@

@@ -74,6 +74,16 @@

 #include "tree-chkp.h"

 #include "tree-chkp.h"

 #include "rtl-chkp.h"

 #include "rtl-chkp.h"

+// #define     DO_ZIP_DEBUGS

+#ifdef DO_ZIP_DEBUGS

+#ifdef DO_ZIP_DEBUGS

+#include <stdio.h>

+#include <stdio.h>

+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)

+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)

+extern void    zip_debug_rtx(const_rtx);

+extern void    zip_debug_rtx(const_rtx);

+#else

+#else

Line 177...

Line 178...

+#endif

+#endif

 /* Some systems use __main in a way incompatible with its use in gcc, in these

 /* Some systems use __main in a way incompatible with its use in gcc, in these

    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to

    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to

    give the same symbol without quotes for an alternative entry point.  You

    give the same symbol without quotes for an alternative entry point.  You

@@ -1172,7 +1181,7 @@

@@ -1172,7 +1182,7 @@

                base_align = crtl->max_used_stack_slot_alignment;

                base_align = crtl->max_used_stack_slot_alignment;

              else

              else

                base_align = MAX (crtl->max_used_stack_slot_alignment,

                base_align = MAX (crtl->max_used_stack_slot_alignment,

-                                 GET_MODE_ALIGNMENT (SImode)

-                                 GET_MODE_ALIGNMENT (SImode)

+                                 GET_MODE_ALIGNMENT (word_mode)

+                                 GET_MODE_ALIGNMENT (word_mode)

                                  << ASAN_SHADOW_SHIFT);

                                  << ASAN_SHADOW_SHIFT);

          else

          else

@@ -2225,7 +2234,7 @@

@@ -2225,7 +2235,7 @@

          data.asan_vec.safe_push (offset);

          data.asan_vec.safe_push (offset);

          /* Leave space for alignment if STRICT_ALIGNMENT.  */

          /* Leave space for alignment if STRICT_ALIGNMENT.  */

          if (STRICT_ALIGNMENT)

          if (STRICT_ALIGNMENT)

-           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)

-           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)

+           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)

+           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)

                                      << ASAN_SHADOW_SHIFT)

                                      << ASAN_SHADOW_SHIFT)

                                     / BITS_PER_UNIT, 1);

                                     / BITS_PER_UNIT, 1);

@@ -5745,7 +5754,7 @@

@@ -5745,7 +5755,7 @@

       && (last = get_last_insn ())

       && (last = get_last_insn ())

       && JUMP_P (last))

       && JUMP_P (last))

-      rtx dummy = gen_reg_rtx (SImode);

-      rtx dummy = gen_reg_rtx (SImode);

+      rtx dummy = gen_reg_rtx (word_mode);

+      rtx dummy = gen_reg_rtx (word_mode);

Line 298...

Line 299...

+#undef TARGET_OPTION_OPTIMIZATION_TABLE

+#undef TARGET_OPTION_OPTIMIZATION_TABLE

+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table

+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table

+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;

+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops gcc-6.2.0-zip/gcc/config/zip/genzipops

--- gcc-6.2.0/gcc/config/zip/genzipops  1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/genzipops      2018-03-22 18:33:09.823726748 -0400

@@ -0,0 +1,201 @@

+ELF>@@�N@8       @@@@@@��88@8@@@�9�9 >>`>`�� (>(>`(>`��TT@T@DDP�td�6�6@�6@��Q�tdR�td>>`>`��/lib64/ld-linux-x86-64.so.2GNU GNU��F3m��+�Z\L�=����<9�4B;#tm^� fWPI�@`libc.so.6exitsprintffopenputs__stack_chk_failunlinkstrlenfclosestderrfwriterenamefprintfaccessstrcmp__libc_start_main__gmon_start__GLIBC_2.4GLIBC_2.2.5ii
�ui      ��?`        �@`@` @`(@`0@`8@`@@`H@`P@`X@`

+`@`h@`p@`
x@`�@`H��H�9 H��t�H����59 �%9 @�%9 h������%�8 h������%�8 h������%�8 h�����%�8 h�����%�8 h�����%�8 h�����%�8 h�p����%�8 h�`����%�8 h     �P����%�8 h

+�@����%�8 h�0����%�8 h� ����%�8 h
�����%8 f�1�I��^H��H���PTI���@H���@H��>@�7����fD��@`UH-�@`H��H��v�H��t]��@`��f�]�@f.���@`UH��@`H��H��H��H��?H�H��t�H��t]��@`��]�fD�=8 uUH���n���]��7 ��@� >`H�?u��H��t�UH����]�z���UH��H��H�}�H�E�H������@��������UH��H��H�}�H�u�H�U�H�E��� @H�Ǹ�6������UH��H��0H�}�H�u�H�U�H�M�L�E�L�M�H�}�H�u�H�M�H�U�H�E�H���u�u��u�I��I��� @H�Ǹ�����H�� ���UH��H���H��h���H��`���H��X���H��P���L��H���L��@���H�EH��8���dH�%(H�E�1�H��8���H��p�����!@H�Ǹ����H��8���H��h�����!@H�Ǹ�D���H��8���H��P���H��X���H��`���H��h���H����`���I��I���!@H�Ǹ�����H��H��8���H��P���H��@���H��`���H��h���H����`���I��I��"@H�Ǹ����H��H��8���H��P���H��@���H��`���H��h���H��h?#@A�<#@I��H���B���H��H��8���H��P���H��@���H��`���H��h���H��hD#@A�A#@I��H������H��H��8���H��P���H��@���H��`���H��h���H��hJ#@A�G#@I��H�������H��H��8���H��P���H��@���H��`���H��h���H��hP#@A�M#@I��H������H��H��8���H��P���H��@���H��`���H��h���H��hW#@A�S#@I��H���>���H��H��8���H��P���H��@���H��`���H��h���H��h]#@A�Y#@I��H�������H���H�E�dH3%(t�������UH��H��H������H������H������H������L������dH�%(H�E�1�H������H�������`#@H�Ǹ�����H������H�������$@H�Ǹ�����H������H�������8$@H�Ǹ����L������H������H������H������H������H������H��������M��I��H���c���H��H������H��������$@H�Ǹ�R���H������H��������%@H�Ǹ�2���H������H��������%@H�Ǹ����H������H��������&@H�Ǹ�����L������H������H������H������H������H������H��������M��I��H������H���H�E�dH3%(t�'�����UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�H���u��u��u�I��I��&@H�Ǹ����H�� ���UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��(@H�Ǹ�������UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��`)@H�Ǹ�r������UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��*@H�Ǹ�+������UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��+@H�Ǹ��������UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I���,@H�Ǹ�������UH��H�� H�}�H�u�H�U�H�M�H�}�H�u�H�M�H�U�H�E�I��I��(.@H�Ǹ�V������UH��p/@������]�UH��AUATSH��(�}�H�u�H�?0 ��/@H���:���H�E�H�/0 H�EЃ}�~!H�E�H��H��<-u������4����}���H�E�H��H�H������H��H��/ H���u���H9�r~H��/ H�E�H��L� H�E�H��H�H���K���I��H��/ H���9���I)�L��L�H��H���U�����u/H�E�H��H��H���Y�����uH�E�H��H�H�������H�E�H�@H�E�H�E�H������H�E�A��/@��/@��/@��/@H�������H�E�A��/@��/@��/@��/@H�������H�E�A��/@��/@��/@��/@H������H�E�A��/@��/@�0@�0@H������H�E�A�0@��/@�0@�0@H���`���H�E�A�$0@��/@�(0@�/0@H���?���H�E�A�60@��/@�90@�@0@H������H�E�A�G0@��/@�K0@�R0@H�������H�E�A�Y0@��/@�]0@�i0@H�������H�E�A�q0@��/@�u0@�0@H������H�E�A��0@��/@��0@��0@H������H�E�H��h3@A��0@A�x1@�

+2@�2@�3@H������H��H�E�H��h�5@A� 3@A��3@�

+2@��4@�5@H���x���H��H�Eؾ�5@H�������H�Eع?#@�<#@��5@H�������H�EعD#@�A#@��5@H������H�EعJ#@�G#@��5@H������H�EعP#@�M#@��5@H���u���H�EعW#@�S#@��5@H���Z���H�Eع]#@�Y#@��5@H���?���H�Eؾ�5@H���#���H�Eع?#@�<#@��5@H���k���H�EعD#@�A#@��5@H���P���H�EعJ#@�G#@��5@H���5���H�EعP#@�M#@��5@H������H�EعW#@�S#@��5@H�������H�Eع]#@�Y#@��5@H�������H�Eؾ�5@H���p���H�Eع?#@�<#@�6@H���F���H�EعD#@�A#@�6@H���+���H�EعJ#@�G#@�6@H������H�EعP#@�M#@�6@H�������H�EعW#@�S#@�6@H�������H�Eع]#@�Y#@�6@H������H�Eؾ6@H������H�Eع?#@�<#@�"6@H���L���H�EعD#@�A#@�"6@H���1���H�EعJ#@�G#@�"6@H������H�EعP#@�M#@�"6@H�������H�EعW#@�S#@�"6@H�������H�Eع]#@�Y#@�"6@H�������H�Eؾ'6@H���

+���H�Eع?#@�<#@�D6@H���'���H�EعD#@�A#@�D6@H������H�EعJ#@�G#@�D6@H�������H�EعP#@�M#@�D6@H�������H�EعW#@�S#@�D6@H������H�Eع]#@�Y#@�D6@H������H�EؾI6@H���W���H�Eع?#@�<#@�f6@H������H�EعD#@�A#@�f6@H������H�EعJ#@�G#@�f6@H������H�EعP#@�M#@�f6@H���j���H�EعW#@�S#@�f6@H���O���H�Eع]#@�Y#@�f6@H���4���H�Eؾk6@H������H�Eع?#@�<#@��6@H���O���H�EعD#@�A#@��6@H���4���H�EعJ#@�G#@��6@H������H�EعP#@�M#@��6@H�������H�EعW#@�S#@��6@H�������H�Eع]#@�Y#@��6@H�������H�E�H������H�g( H�U�H��H���p�����t.H�
M( H�n( H�Uо�6@H�Ǹ������^�����T���@AWAVA��AUATL�%~% UH�-~% SI��I��L)�H��H���'���H��t 1��L��L��D��A��H��H9�u�H��[]A\A]A^A_Ðf.���H��H���;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Filename:   zip-ops.md

+;;

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;;

+;; Purpose:    This is a computer generated machine description of the

+;;             ZipCPU's operations.  It is computer generated simply for

+;;     two reasons.  First, I can't seem to find a way to generate this

+;;     information within GCC's current constructs.  Specifically, the

+;;     CPU's instructions normally set the condition codes, unless they

+;;     are conditional instructions when they don't.  Second, the ZipCPU is

+;;     actually quite regular.  Almost all of the instructions have the same

+;;     form.  This form turns into many, many RTL instructions.  Because the

+;;     CPU doesn't match any of the others within GCC, that means either

+;;     I have a *lot* of cut, copy, paste, and edit to do to create the file

+;;     and upon any and every edit, or I need to build a program to generate

+;;     the remaining .md constructs.  Hence, I chose the latter to minimize

+;;     the amount of work I needed to do.

+;;

+;;

+;; Creator:    Dan Gisselquist, Ph.D.

+;;             Gisselquist Technology, LLC

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Copyright (C) 2017, Gisselquist Technology, LLC

+;;

+;; This program is free software (firmware): you can redistribute it and/or

+;; modify it under the terms of  the GNU General Public License as published

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; your option) any later version.

+;;

+;; This program is distributed in the hope that it will be useful, but WITHOUT

+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

+;; for more details.

+;;

+;; License:    GPL, v3, as defined and found on www.gnu.org,

+;;             http://www.gnu.org/licenses/gpl.html

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;

+;

+; %s

+;

+;

+(define_insn "%s_%s"

+       [(cond_exec (%s (reg:CC CC_REG) (const_int 0))

+                       %s)]

+       "%s"    ; Condition

+       "%s.%s\t%%1,%%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+%s (genzipop_long);

+;

+;

+; %s (genzipop_long)

+;

+;

+;

+(define_insn "%s"

+       [%s

+       (clobber (reg:CC CC_REG))]

+       "%s"

+       "%s\t%%2,%%0    ; %s"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "%s_raw"

+       [%s

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "%s"

+       "%s\t%%1,%%0    ; %s_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+eqZneNZltLTgeGEltuCgeuNC(set (match_operand:SI 0 "register_operand" "=r")

+               (%s (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))(set (match_operand:SI 0 "register_operand" "=r")

+               (%s (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))(set (match_operand:SI 0 "register_operand" "=r")

+               (%s (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))(set (match_dup 0) (%s (match_dup 0)

+                       (plus:SI (match_dup 2) (match_dup 3))))(set (match_operand:SI 0 "register_operand" "=r")

+               (%s (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))%s_off;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.%s  %%1,%%0 ; cmov

+       LW.%s   %%1,%%0 ; cmov

+       LDI.%s  %%1,%%0 ; cmov

+       SW.%s   %%1,%%0 ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.%s %%1,%%0 ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.%s %%0     ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.%s %%0     ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.%s %%1,%%0 ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.%s  %%1,%%0 ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "%s_%s"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.%s %%1,%%0 ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+USAGE: genzipops <new-zip-ops.md filename>.zip-ops.mdzip-ops.mdwADDplus:SIaddsi3SUBminus:SIsubsi3MPYmult:SImulsi3DIVS(ZIP_DIVIDE)div:SIdivsi3DIVUudiv:SIudivsi3ANDand:SIandsi3ORior:SIiorsi3XORxor:SIxorsi3ASRashiftrt:SIashrsi3LSLashift:SIashlsi3LSRlshiftrt:SIlshrsi3(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))(set (match_dup 0)

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 1))

+                       (sign_extend:DI (match_dup 2)))

+                       (const_int 32))))(ZIP_HAS_DI)(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))

+                       (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))smulsi_highpartMPYSHI(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))(set (match_dup 0)

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 1))

+                       (zero_extend:DI (match_dup 2)))

+                       (const_int 32))))(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))

+                       (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))umulsi_highpartMPYUHIConditional move instructionscmovConditional add instructionscaddConditional negate instructionscnegConditional not instructionscnotConditional and instructionscandConditional ior instructionsciorConditional xor instructionscxorERR: Could not create %s, leaving results in %s

+;�<����<����2���\���,����L����l�����g�������������M�������,����L"���li����z���������,���zRx�����*zRx�$P����FJw�?;*3$"D���*A�C
ed(���-A�C
h�5���`A�C
[�u����A�C
������A�C
������XA�C
S����GA�C
B$���GA�C
BD9���GA�C
Bd`���GA�C
B�����GA�C
B�����GA�C
B�����A�C
L�����>A�C
I���D����eB�B�E �B(�H0�H8�M@r8A0A(B BBBL����@�@�@
�@>`>`���o�@X@�@

+�@`P�@X@0        ���o(@���o���o@(>`@&@6@F@V@f@v@�@�@�@�@�@�@�@�/@�/@GCC: (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 201606098@T@t@�@�@X@@(@   X@

+�@�@@
�@@�@@�6@`7@>`>` >`(>`�?`@`�@`�@`�� >`0@p@.�@D�@`S>`z�@�>`�������9@� >`���>`�(>`�>`��6@@`!�@1�@G9M - �@`i+@Xq��@`�k@��M     @`��@`��@`�+�@���� @��@G+�@`8LX@GTi x�@`�@��@e��@`�  @-1@*��@G��@G��@`�>@>�-@��� &�@*,ASg�@`s �@G��@��@`crtstuff.c__JCR_LIST__deregister_tm_clones__do_global_dtors_auxcompleted.7594__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entrygenzipops.c__FRAME_END____JCR_END____init_array_end_DYNAMIC__init_array_start__GNU_EH_FRAME_HDR_GLOBAL_OFFSET_TABLE___libc_csu_finigenciorunlink@@GLIBC_2.2.5_ITM_deregisterTMCloneTablegencmovputs@@GLIBC_2.2.5TAILPATHgenzipopgenzip_condopTMPPATH_edatafclose@@GLIBC_2.2.5strlen@@GLIBC_2.2.5__stack_chk_fail@@GLIBC_2.4genzipop_longgencnot__libc_start_main@@GLIBC_2.2.5__data_startstrcmp@@GLIBC_2.2.5gencandfprintf@@GLIBC_2.2.5__gmon_start____dso_handle_IO_stdin_used__libc_csu_initgen_headinggencxorgencadd__bss_startmainusageaccess@@GLIBC_2.2.5fopen@@GLIBC_2.2.5_Jv_RegisterClassesrename@@GLIBC_2.2.5legalsprintf@@GLIBC_2.2.5exit@@GLIBC_2.2.5fwrite@@GLIBC_2.2.5__TMC_END___ITM_registerTMCloneTablegencnegstderr@@GLIBC_2.2.5.symtab.strtab.shstrtab.interp.note.ABI-tag.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.got.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.jcr.dynamic.got.plt.data.bss.comment8@8#T@T 1t@t$D���o�@�$N�@��VX@X�^���o@"k���o(@(0zX@X0�B�@�P��@��@���@��@���@�  �@���6@�6��`7@`7��>`>�>`>� >` >�(>`(>���?`�?�@`@���@`�@ ��@`�@ 0�@4qM�@�/ �I�

\ No newline at end of file

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c

--- gcc-6.2.0/gcc/config/zip/genzipops.c        1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/genzipops.c        1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c    2017-03-07 12:03:59.062584503 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c    2017-03-07 12:03:59.062584503 -0500

@@ -0,0 +1,444 @@

@@ -0,0 +1,444 @@

+////////////////////////////////////////////////////////////////////////////////

+////////////////////////////////////////////////////////////////////////////////

Line 748...

Line 955...

+               exit(EXIT_FAILURE);

+               exit(EXIT_FAILURE);

+       } exit(EXIT_SUCCESS);

+       } exit(EXIT_SUCCESS);

+}

+}

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c

--- gcc-6.2.0/gcc/config/zip/zip.c      1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/zip.c      1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.c  2017-03-07 12:03:18.566583672 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.c  2018-06-05 21:17:24.151098201 -0400

@@ -0,0 +1,2679 @@

@@ -0,0 +1,2711 @@

+////////////////////////////////////////////////////////////////////////////////

+////////////////////////////////////////////////////////////////////////////////

+//

+//

+// Filename:   zip.c

+// Filename:   zip.c

+//

+//

+// Project:    Zip CPU backend for the GNU Compiler Collection

+// Project:    Zip CPU backend for the GNU Compiler Collection

Line 2500...

Line 2707...

+                       strcpy(mstr, ":QI");

+                       strcpy(mstr, ":QI");

+               else if (GET_MODE(x) == HImode)

+               else if (GET_MODE(x) == HImode)

+                       strcpy(mstr, ":HI");

+                       strcpy(mstr, ":HI");

+               else if (GET_MODE(x) == SImode)

+               else if (GET_MODE(x) == SImode)

+                       strcpy(mstr, ":SI");

+                       strcpy(mstr, ":SI");

+               else if (GET_MODE(x) == DImode)

+                       strcpy(mstr, ":DI");

+               else if (GET_MODE(x) == SFmode)

+                       strcpy(mstr, ":SF");

+               else if (GET_MODE(x) == DFmode)

+                       strcpy(mstr, ":DF");

+               else if (GET_MODE(x) == VOIDmode)

+               else if (GET_MODE(x) == VOIDmode)

+                       strcpy(mstr, ":V");

+                       strcpy(mstr, ":V");

+               else

+               else

+                       strcpy(mstr, ":?");

+                       strcpy(mstr, ":?");

+               if (REG_P(XEXP(x,0))) {

+               if (REG_P(XEXP(x,0))) {

+                       int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),

+                       int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),

+                               sb = SUBREG_BYTE(x);

+                               sb = SUBREG_BYTE(x);

+                       if (mod==QImode)

+                       if (mod==SFmode)

+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);

+                       sprintf(buf,"(SUBREG%s (REG:SF %d)/%d)",mstr,hreg, sb);

+                       else if (mod==DFmode)

+                       sprintf(buf,"(SUBREG%s (REG:DF %d)/%d)",mstr,hreg, sb);

+                       else if (mod==DImode)

+                       sprintf(buf,"(SUBREG%s (REG:DI %d)/%d)",mstr,hreg, sb);

+                       else if (mod==SImode)

+                       sprintf(buf,"(SUBREG%s (REG:SI %d)/%d)",mstr,hreg, sb);

+                       else if (mod==HImode)

+                       else if (mod==HImode)

+                       sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);

+                       sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);

+                       else if (mod==QImode)

+                       else if (mod==QImode)

+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);

+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);

+                       else if (mod==VOIDmode)

+                       else if (mod==VOIDmode)

Line 2944...

Line 3163...

+               emit_insn(gen_movdi_raw(dst, src));

+               emit_insn(gen_movdi_raw(dst, src));

+               return 1;

+               return 1;

+       }

+       }

+       // MOV SUBREG->REG

+       if ((REG_P(dst))&&(SUBREG_P(src))) {

+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- SUBREG->REG\n");

+               if (GET_MODE(src)==DImode) {

+                       emit_insn(gen_movdi_raw(dst, src));

+                       return 1;

+               }

+       }

+       // MOV REG->SUBREG

+       if ((SUBREG_P(dst))&&(REG_P(src))) {

+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->SUBREG\n");

+               if (GET_MODE(dst)==DImode) {

+                       emit_insn(gen_movdi_raw(dst, src));

+                       return 1;

+               }

+       }

+       // MOV REG->MEM (a store instruction)

+       // MOV REG->MEM (a store instruction)

+       if ((MEM_P(dst))&&(REG_P(src))) {

+       if ((MEM_P(dst))&&(REG_P(src))) {

+               rtx     addr = XEXP(dst,0);

+               rtx     addr = XEXP(dst,0);

+               long    offset = 0;

+               long    offset = 0;

+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))

+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))

Line 3443...

Line 3682...

+#else

+#else

+#define        ZIP_DEBUG_LINE(STR,RTX)

+#define        ZIP_DEBUG_LINE(STR,RTX)

+#endif

+#endif

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md

--- gcc-6.2.0/gcc/config/zip/zip-di.md  1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/zip-di.md  1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md      2017-02-22 15:56:17.195319460 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md      2018-06-05 18:57:29.386399718 -0400

@@ -0,0 +1,528 @@

@@ -0,0 +1,548 @@

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Filename:   zip-di.md

+;; Filename:   zip-di.md

+;;

+;;

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

Line 3462...

Line 3701...

+;; Creator:    Dan Gisselquist, Ph.D.

+;; Creator:    Dan Gisselquist, Ph.D.

+;;             Gisselquist Technology, LLC

+;;             Gisselquist Technology, LLC

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Copyright (C) 2015, Gisselquist Technology, LLC

+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC

+;;

+;;

+;; This program is free software (firmware): you can redistribute it and/or

+;; This program is free software (firmware): you can redistribute it and/or

+;; modify it under the terms of  the GNU General Public License as published

+;; modify it under the terms of  the GNU General Public License as published

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; your option) any later version.

+;; your option) any later version.

Line 3506...

Line 3745...

+       {

+       {

+               if ((REG_P(operands[0]))&&(REG_P(operands[1])))

+               if ((REG_P(operands[0]))&&(REG_P(operands[1])))

+                       return  "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";

+                       return  "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";

+               else if (MEM_P(operands[0]))    //; StoreDI

+               else if (MEM_P(operands[0]))    //; StoreDI

+                       return  "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";

+                       return  "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";

+               else if (MEM_P(operands[1]))    //; LoadDI

+               else if (MEM_P(operands[1])) {  //; LoadDI

+                       //; Deal with the case of

+                       //;     LOD (R0),R0

+                       //;     LOD 4(R0),R1

+                       //; By reversing the order of the operands, to

+                       //;     LOD 4(R0),R1

+                       //;     LOD (R0),R0

+                       //; This isn't efficient, so let's do whatever we can to

+                       //; avoid this, still ... if we do it, we can make it

+                       //; work

+                       rtx     address = XEXP(operands[1],0);

+                       int     hazard = 0;

+                       if ( (REG_P(address))

+                               &&((REGNO(address))==(REGNO(operands[0]))) )

+                               hazard = 1;

+                       else if ( (PLUS == (GET_CODE(address)))

+                               &&(REGNO(XEXP(address,0))==(REGNO(operands[0]))) )

+                               hazard = 1;

+                       if (hazard)

+                               return  "LW 4+%1,%L0\t; Load:DI\n\tLW %1,%H0";

+                       else

+                       return  "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";

+                       return  "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";

+               else if (CONST_INT_P(operands[1])) {

+               } else if (CONST_INT_P(operands[1])) {

+                       char    tmp[128];

+                       char    tmp[128];

+                       HOST_WIDE_INT   v = INTVAL(operands[1]);

+                       HOST_WIDE_INT   v = INTVAL(operands[1]);

+                       sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",

+                       sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",

+                               (unsigned)(v>>32),

+                               (unsigned)(v>>32),

+                               (unsigned)(v));

+                               (unsigned)(v));

Line 4117...

Line 4376...

+;

+;

+;

+;

+;

+;

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h

--- gcc-6.2.0/gcc/config/zip/zip.h      1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/zip.h      1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.h  2017-03-03 09:30:57.671304970 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.h  2018-06-05 22:22:38.581639662 -0400

@@ -0,0 +1,4114 @@

@@ -0,0 +1,4114 @@

+////////////////////////////////////////////////////////////////////////////////

+////////////////////////////////////////////////////////////////////////////////

+//

+//

+// Filename:   gcc/config/zip/zip.h

+// Filename:   gcc/config/zip/zip.h

+//

+//

Line 4314...

Line 4573...

+ * line.  This constant is placed both before and after the value of LIB_SPEC.

+ * line.  This constant is placed both before and after the value of LIB_SPEC.

+ *

+ *

+ * If this macro is not defined, the GCC driver provides a default that passes

+ * If this macro is not defined, the GCC driver provides a default that passes

+ * the string '-lgcc' to the linker.

+ * the string '-lgcc' to the linker.

+ */

+ */

+#undef LIBGCC_SPEC

+// #undef      LIBGCC_SPEC

+#define        LIBGCC_SPEC     ""

+// #define     LIBGCC_SPEC     ""

+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the

+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the

+ * LIBGCC_SPEC is not directly used by the driver program but is instead

+ * LIBGCC_SPEC is not directly used by the driver program but is instead

+ * modified to refer to different versions of 'libgcc.a' depending on the

+ * modified to refer to different versions of 'libgcc.a' depending on the

+ * values of the command line flags '-static', '-shared', '-static-libgcc',

+ * values of the command line flags '-static', '-shared', '-static-libgcc',

Line 4388...

Line 4647...

+ * command line parameters we've been given indicate that our CPU has.  That

+ * command line parameters we've been given indicate that our CPU has.  That

+ * way, code can be adjusted depending upon the CPU's capabilities.

+ * way, code can be adjusted depending upon the CPU's capabilities.

+ */

+ */

+#define        TARGET_CPU_CPP_BUILTINS()                               \

+#define        TARGET_CPU_CPP_BUILTINS()                               \

+       { builtin_define("__ZIPCPU__");                         \

+       { builtin_define("__ZIPCPU__");                         \

+       builtin_define("__BIG_ENDIAN__");                       \

+       builtin_define("__IEEE_BIG_ENDIAN");                    \

+       builtin_define("__IEEE_BIG_ENDIAN");                    \

+       builtin_define("_LDBL_EQ_DBL");                         \

+       builtin_define("_LDBL_EQ_DBL");                         \

+       if (ZIP_FPU) builtin_define("__ZIPFPU__");              \

+       if (ZIP_FPU) builtin_define("__ZIPFPU__");              \

+       else builtin_define("_SOFT_FLOAT");                     \

+       else builtin_define("_SOFT_FLOAT");                     \

+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \

+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \

Line 4440...

Line 4700...

+ * ZipCPU floating point is barely going to be functional, I doubt it will

+ * ZipCPU floating point is barely going to be functional, I doubt it will

+ * support all of these bells and whistles when full functionality is even

+ * support all of these bells and whistles when full functionality is even

+ * achieved.  Therefore, we won't support these modes.  However, we can't just

+ * achieved.  Therefore, we won't support these modes.  However, we can't just

+ * set this to zero, so let's come back to this.

+ * set this to zero, so let's come back to this.

+ */

+ */

+// #warning "Wrong answer encoded to date"

+// #undef      TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P

+// #undef      TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P

+// #define     TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0

+// #define     TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0

+/* 17.04 Defining data structures for per-function information */

+/* 17.04 Defining data structures for per-function information */

Line 7158...

Line 7417...

+ * efficient.

+ * efficient.

+ */

+ */

+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive

+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive

+ * to specify the size of a symbol, without any arguments.  ON systems that

+ * to specify the size of a symbol, without any arguments.  ON systems that

+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to

+ * use ELF, the default is "\t.size\t"; on other systems, the default is not to

+ * define this macro.

+ * define this macro.

+ *

+ *

+ * Define this amcro only if it is correct to use the default definitions of

+ * Define this amcro only if it is correct to use the default definitions of

+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.

+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.

+ * If you need your own custom definitions of those macros, or if you do not

+ * If you need your own custom definitions of those macros, or if you do not

Line 7214...

Line 7473...

+ */

+ */

+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement

+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement

+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for

+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for

+ * claiming a register REGNO for a global variable DECL with name NAME.

+ * claiming a register REGNO for a global variable DECL with name NAME.

+ *

+ *

+ * If you don't defin this macro, that is equivalent to dfining it to do

+ * If you don't defin this macro, that is equivalent to defining it to do

+ * nothing.

+ * nothing.

+ */

+ */

+/* ASM_FINISH_DECLARE_OBJECT

+/* ASM_FINISH_DECLARE_OBJECT

+ * TARGET_ASM_GLOBALIZE_LABEL

+ * TARGET_ASM_GLOBALIZE_LABEL

Line 8235...

Line 8494...

+#endif /* GCC_ZIP_H */

+#endif /* GCC_ZIP_H */

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md

--- gcc-6.2.0/gcc/config/zip/zip.md     1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/zip.md     1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2017-03-07 12:02:29.862582673 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2018-06-07 12:51:05.802342817 -0400

@@ -0,0 +1,1968 @@

@@ -0,0 +1,1897 @@

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Filename:   zip.md

+;; Filename:   zip.md

+;;

+;;

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

Line 8252...

Line 8511...

+;; Creator:    Dan Gisselquist, Ph.D.

+;; Creator:    Dan Gisselquist, Ph.D.

+;;             Gisselquist Technology, LLC

+;;             Gisselquist Technology, LLC

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Copyright (C) 2015-2017, Gisselquist Technology, LLC

+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC

+;;

+;;

+;; This program is free software (firmware): you can redistribute it and/or

+;; This program is free software (firmware): you can redistribute it and/or

+;; modify it under the terms of  the GNU General Public License as published

+;; modify it under the terms of  the GNU General Public License as published

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; your option) any later version.

+;; your option) any later version.

Line 8335...

Line 8594...

+(define_constants

+(define_constants

+  [(RTN_REG            0)      ; Return address register

+  [(RTN_REG            0)      ; Return address register

+   (RTNV_REG           1)      ; Subroutine return value register

+   (RTNV_REG           1)      ; Subroutine return value register

+   (AP_REG             10)     ; Hopefully never used

+   (AP_REG             10)     ; Hopefully never used

+   (GBL_REG            11)     ; Hopefully never used, but just in case ...

+   (GBL_REG            11)     ; Hopefully never used, but just in case ...

+   (FP_REG             12)

+   (FP_REG             12)     ; Frame pointer register

+   (SP_REG             13)

+   (SP_REG             13)     ; Stack pointer register

+   (CC_REG             14)

+   (CC_REG             14)     ; Condition codes register

+   (PC_REG             15)

+   (PC_REG             15)     ; Program counter

+  ])

+  ])

+;

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

Line 8418...

Line 8677...

+{

+{

+       return zip_pd_mvimm_operand(op);

+       return zip_pd_mvimm_operand(op);

+})

+})

+;

+;

+; zip_movdst_operand_p and zip_movsrc_operand_p are no longer necessary, and

+; are being deprecated.

+;

+;(define_predicate "zip_movdst_operand_p"

+;      (match_code "mem,reg,subreg")

+;{

+;      if (MEM_P(op)) // Check for valid store address

+;              return zip_pd_opb_operand(XEXP(op,0));

+;      else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0))))

+;              return 1;

+;      else if (REG_P(op))

+;              return register_operand(op, GET_MODE(op));

+;      return 1;

+;})

+;(define_predicate "zip_movsrc_operand_p"

+;      (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")

+;{

+;      if (MEM_P(op))

+;              return zip_pd_opb_operand(XEXP(op,0));

+;      else if (GET_CODE(op)==PLUS)

+;              return zip_pd_opb_operand(op);

+;      else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0)))) {

+;              //; As far as predicates are concerned, subregs must be valid.

+;              //; The details of them are settled within the constraints.

+;              return 1;

+;      } else if ((REG_P(op))||(SUBREG_P(op)))

+;              return register_operand(op,SImode);

+;      else if (CONST_INT_P(op))

+;              return 1;

+;      return 1;

+;})

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Constraints

+;; Constraints

Line 8629...

Line 8854...

+;

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Load and store multiple values

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+; So far, from the code I've seen from GCC's output,

+; these instructions do not appear to be necessary.

+;

+;(define_insn "load_multiple"

+;      for(a=0; a<%2; a++)

+;              LW a(%1),%0+a

+;(define_insn "store_multiple"

+;      for(a=0; a<%2; a++)

+;              SW %0+a,a(%1)

+; pushsi -- Do not define, compiler will work around it nicely w/o our help

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Substitution Pattern

+;; Substitution Pattern

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+;

+;

+;

Line 8838...

Line 9043...

+;; (define_insn "umulvsi4"

+;; (define_insn "umulvsi4"

+;;     ... ???)

+;;     ... ???)

+;;

+;;

+;

+;

+;

+;

+; ASR

+; LSL

+; LSR

+;

+;

+;

+;

+;

+;

+;

+;

+;

+; Others:  NEG, TEST, POPC, NOT

+; Others:  NEG, TEST, POPC, NOT

Line 8881...

Line 9082...

+;

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Conditional arithmetic instructions

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+;

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Comparison instructions, both compare and test

+;; Comparison instructions, both compare and test

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+;

+;

+;

Line 9071...

Line 9260...

+(define_expand "notsicc"

+(define_expand "notsicc"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (match_operand 1 "comparison_operator")

+               (if_then_else:SI (match_operand 1 "comparison_operator")

+                       (xor:SI (match_operand:SI 2 "register_operand" "0")

+                       (xor:SI (match_operand:SI 2 "register_operand" "0")

+                               (const_int -1))

+                               (const_int -1))

+                       (match_dup 2)))]

+                       (match_operand:SI 3 "register_operand" "0")))]

+       ""

+       ""

+       {

+       {

+               extern void zip_debug_rtx_pfx(const char *, const_rtx);

+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);

+               //; fprintf(stderr, "NOTSICC\n");

+               //; fprintf(stderr, "NOTSICC\n");

+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);

+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);

+               //; zip_debug_rtx_pfx("- CMP: ", operands[1]);

+               //; zip_debug_rtx_pfx("- CMP: ", operands[1]);

+               //; zip_debug_rtx_pfx("- NOT: ", operands[2]);

+               //; zip_debug_rtx_pfx("- NOT: ", operands[2]);

+               //; zip_debug_rtx_pfx("- OLD: ", operands[3]);

+               //; zip_debug_rtx_pfx("- OLD: ", operands[3]);

+               if (!REG_P(operands[2]))

+                       operands[2] = force_reg(SImode, operands[2]);

+               if (REGNO(operands[0]) != REGNO(operands[2]))

+                       emit_insn(gen_movsi(operands[0], operands[2]));

+               rtx_code        ccode = GET_CODE(operands[1]);

+               rtx_code        ccode = GET_CODE(operands[1]);

+               rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));

+               rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));

+               rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));

+               rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));

Line 10136...

Line 10321...

+       [(trap_if (const_int 1) (const_int 0))]

+       [(trap_if (const_int 1) (const_int 0))]

+       ""

+       ""

+       "BREAK"

+       "BREAK"

+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])

+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+(define_expand "ctrapsi4"

+(define_expand "ctrapsi4"

+       [(set (reg:CC CC_REG) (compare:CC

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 1 "register_operand" "r")

+               (match_operand:SI 1 "register_operand" "r")

+               (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+               (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (trap_if (match_operator 0 "ordered_comparison_operator"

+       (trap_if (match_operator 0 "ordered_comparison_operator"

+                       [(reg:CC CC_REG) (const_int 0)])

+                       [(reg:CC CC_REG) (const_int 0)])

+                       (match_operand 3 "const_int_operand" "O"))]

+                       (match_operand 3 "const_int_operand" "O"))]

+       ""

+       ""

+       )

+       )

+;

+;

+(define_insn "trapif"

+(define_insn "trapif"

+       [(trap_if (match_operator 0 "ordered_comparison_operator"

+       [(trap_if (match_operator 0 "ordered_comparison_operator"

+                       [(reg:CC CC_REG) (const_int 0)])

+                       [(reg:CC CC_REG) (const_int 0)])

+                       (match_operand 1 "const_int_operand" "O"))]

+                       (match_operand 1 "const_int_operand" "O"))]

+       ""

+       ""

Line 10205...

Line 10393...

+;              MOV %ID,R0

+;              MOV %ID,R0

+;              CLR     CC

+;              CLR     CC

+;      cmove   ... the conditional move, created from a

+;      cmove   ... the conditional move, created from a

+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))

+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))

+;      pattern

+;      pattern

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-modes.def gcc-6.2.0-zip/gcc/config/zip/zip-modes.def

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-ops.md gcc-6.2.0-zip/gcc/config/zip/zip-ops.md

--- gcc-6.2.0/gcc/config/zip/zip-modes.def      1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/gcc/config/zip/zip-ops.md 1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-modes.def  2017-01-10 12:46:54.791966242 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-ops.md     2018-03-22 18:33:11.175718614 -0400

@@ -0,0 +1 @@

@@ -0,0 +1,2744 @@

+#define        BITS_PER_UNIT   8

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-peephole.md gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md

--- gcc-6.2.0/gcc/config/zip/zip-peephole.md    1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md        2017-03-01 15:46:02.440221158 -0500

@@ -0,0 +1,768 @@

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Filename:   zip-peephole.md

+;; Filename:   zip-ops.md

+;;

+;;

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;;

+;;

+;; Purpose:    This is a machine description of a variety of peephole

+;; Purpose:    This is a computer generated machine description of the

+;;             optimizations which can be applied to the ZipCPU RTL

+;;             ZipCPU's operations.  It is computer generated simply for

+;;     representation.

+;;     two reasons.  First, I can't seem to find a way to generate this

+;;     information within GCC's current constructs.  Specifically, the

+;;     CPU's instructions normally set the condition codes, unless they

+;;     are conditional instructions when they don't.  Second, the ZipCPU is

+;;     actually quite regular.  Almost all of the instructions have the same

+;;     form.  This form turns into many, many RTL instructions.  Because the

+;;     CPU doesn't match any of the others within GCC, that means either

+;;     I have a *lot* of cut, copy, paste, and edit to do to create the file

+;;     and upon any and every edit, or I need to build a program to generate

+;;     the remaining .md constructs.  Hence, I chose the latter to minimize

+;;     the amount of work I needed to do.

+;;

+;;

+;;

+;;

+;; Creator:    Dan Gisselquist, Ph.D.

+;; Creator:    Dan Gisselquist, Ph.D.

+;;             Gisselquist Technology, LLC

+;;             Gisselquist Technology, LLC

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC

+;; Copyright (C) 2017, Gisselquist Technology, LLC

+;;

+;;

+;; This program is free software (firmware): you can redistribute it and/or

+;; This program is free software (firmware): you can redistribute it and/or

+;; modify it under the terms of  the GNU General Public License as published

+;; modify it under the terms of  the GNU General Public License as published

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; your option) any later version.

+;; your option) any later version.

Line 10248...

Line 10441...

+;;             http://www.gnu.org/licenses/gpl.html

+;;             http://www.gnu.org/licenses/gpl.html

+;;

+;;

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;;

+;;

+;

+;

+;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+; ADD (genzipop_long)

+;;

+;; Peephole optimizations

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+;

+;

+;

+;

+;

+(define_insn "addsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "ADD\t%2,%0     ; addsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+;

+;

+; Match:

+(define_insn "addsi3_raw"

+;      CMP     R1,R0

+       [(set (match_operand:SI 0 "register_operand" "=r")

+;      BGTU    lbl

+               (plus:SI (match_dup 0)

+; Transform to:

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+;      CMP     R0,R1

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+;      BC      lbl

+       ""

+       "ADD\t%1,%0     ; addsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_peephole2

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 0 "register_operand")

+               (match_operand:SI 1 "register_operand")))

+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_operand 2 ""))

+                       (pc)))]

+       "(ZIP_PEEPHOLE)"

+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+(define_peephole2

+       [(match_scratch:SI 3 "=r")

+       (set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 0 "register_operand")

+               (match_operand 1 "const_int_operand")))

+       (match_dup 3)

+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_operand 2 ""))

+                       (pc)))]

+       "(ZIP_PEEPHOLE)"

+       [(set (match_dup 3) (match_dup 1))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+;(define_peephole2

+;      [(set (reg:CC CC_REG) (compare:CC

+;              (match_operand:SI 0 "register_operand")

+;              (match_operand 1 "const_int_operand")))

+;      (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+;                      (label_ref (match_operand 2 ""))

+;                      (pc)))]

+;      ""

+;      [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))

+;      (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))

+;                      (label_ref (match_dup 2))

+;                      (pc)))]

+;      "operands[1] = GEN_INT(INTVAL(operands[1])-1);")

+;

+;

+(define_insn "addsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ADD.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Match:

+;      CMP     R1,R0

+;      BGEU    lbl

+; Transform to:

+;      CMP     1(R0),R1

+;      BC      lbl

+;

+;

+(define_peephole2

+(define_insn "addsi3_ne"

+       [(set (reg:CC CC_REG) (compare:CC

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+               (match_operand:SI 0 "register_operand")

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (match_operand:SI 1 "register_operand")))

+               (plus:SI (match_dup 0)

+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+                       (label_ref (match_operand 2 ""))

+       ""      ; Condition

+                       (pc)))]

+       "ADD.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       "(ZIP_PEEPHOLE)"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_dup 1) (plus:SI (match_dup 0) (const_int 1))))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+;

+;

+;

+;

+; Match:

+(define_insn "addsi3_lt"

+;      CMP     R1,R0

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+;      BGE     lbl

+                       (set (match_operand:SI 0 "register_operand" "=r")

+; Transform to:

+               (plus:SI (match_dup 0)

+;      CMP     1(R0),R1

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+;      BLT     lbl

+       ""      ; Condition

+; ... why?  when we support a BGE instruction?

+       "ADD.LT\t%1,%0  ; genzip, conditional operator" ; Template

+;(define_peephole2

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+       ;[(set (reg:CC CC_REG) (compare:CC

+;

+               ;(match_operand:SI 0 "register_operand")

+;

+               ;(match_operand:SI 1 "register_operand")))

+(define_insn "addsi3_ge"

+       ;(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       ;(label_ref (match_operand 2 ""))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+                       ;(pc)))]

+               (plus:SI (match_dup 0)

+       ;"(ZIP_PEEPHOLE)"

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ;[(set (reg:CC CC_REG) (compare:CC (match_dup 1)

+       ""      ; Condition

+       "ADD.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ADD.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ADD.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; ADD (genzipop_long)

+;

+;

+;

+(define_insn "addsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "ADD\t%2,%0     ; addsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "addsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "ADD\t%1,%0     ; addsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "addsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "addsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (plus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ADD.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; SUB (genzipop_long)

+;

+;

+;

+(define_insn "subsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "SUB\t%2,%0     ; subsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "subsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "SUB\t%1,%0     ; subsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "subsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "SUB.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; SUB (genzipop_long)

+;

+;

+;

+(define_insn "subsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "SUB\t%2,%0     ; subsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "subsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "SUB\t%1,%0     ; subsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "subsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "subsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (minus:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "SUB.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; MPY (genzipop_long)

+;

+;

+;

+(define_insn "mulsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "MPY\t%2,%0     ; mulsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "mulsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "MPY\t%1,%0     ; mulsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "mulsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "MPY.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; MPY (genzipop_long)

+;

+;

+;

+(define_insn "mulsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "MPY\t%2,%0     ; mulsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "mulsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "MPY\t%1,%0     ; mulsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "mulsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "mulsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (mult:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "MPY.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; DIVS (genzipop_long)

+;

+;

+;

+(define_insn "divsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_DIVIDE)"

+       "DIVS\t%2,%0    ; divsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "divsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_DIVIDE)"

+       "DIVS\t%1,%0    ; divsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "divsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.Z\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.C\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; DIVS (genzipop_long)

+;

+;

+;

+(define_insn "divsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_DIVIDE)"

+       "DIVS\t%2,%0    ; divsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "divsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_DIVIDE)"

+       "DIVS\t%1,%0    ; divsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "divsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.Z\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.C\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "divsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (div:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; DIVU (genzipop_long)

+;

+;

+;

+(define_insn "udivsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_DIVIDE)"

+       "DIVU\t%2,%0    ; udivsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "udivsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_DIVIDE)"

+       "DIVU\t%1,%0    ; udivsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "udivsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.Z\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.C\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; DIVU (genzipop_long)

+;

+;

+;

+(define_insn "udivsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_DIVIDE)"

+       "DIVU\t%2,%0    ; udivsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "udivsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_DIVIDE)"

+       "DIVU\t%1,%0    ; udivsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "udivsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.Z\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.C\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "udivsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (udiv:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       "(ZIP_DIVIDE)"  ; Condition

+       "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; AND (genzipop_long)

+;

+;

+;

+(define_insn "andsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "AND\t%2,%0     ; andsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "andsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "AND\t%1,%0     ; andsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "andsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "AND.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; AND (genzipop_long)

+;

+;

+;

+(define_insn "andsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "AND\t%2,%0     ; andsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "andsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "AND\t%1,%0     ; andsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "andsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "andsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (and:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "AND.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; OR (genzipop_long)

+;

+;

+;

+(define_insn "iorsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "OR\t%2,%0      ; iorsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "iorsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "OR\t%1,%0      ; iorsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "iorsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.Z\t%1,%0    ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.NZ\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.LT\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.GE\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.C\t%1,%0    ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "OR.NC\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; OR (genzipop_long)

+;

+;

+;

+(define_insn "iorsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "OR\t%2,%0      ; iorsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "iorsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "OR\t%1,%0      ; iorsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "iorsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.Z\t%1,%0    ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.NZ\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.LT\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.GE\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.C\t%1,%0    ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "iorsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ior:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "OR.NC\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; XOR (genzipop_long)

+;

+;

+;

+(define_insn "xorsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "XOR\t%2,%0     ; xorsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "xorsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "XOR\t%1,%0     ; xorsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "xorsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "XOR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; XOR (genzipop_long)

+;

+;

+;

+(define_insn "xorsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "XOR\t%2,%0     ; xorsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "xorsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "XOR\t%1,%0     ; xorsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "xorsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "xorsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (xor:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "XOR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; ASR (genzipop_long)

+;

+;

+;

+(define_insn "ashrsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "ASR\t%2,%0     ; ashrsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashrsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "ASR\t%1,%0     ; ashrsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashrsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "ASR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; ASR (genzipop_long)

+;

+;

+;

+(define_insn "ashrsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "ASR\t%2,%0     ; ashrsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashrsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "ASR\t%1,%0     ; ashrsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashrsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashrsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "ASR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; LSL (genzipop_long)

+;

+;

+;

+(define_insn "ashlsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "LSL\t%2,%0     ; ashlsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashlsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "LSL\t%1,%0     ; ashlsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashlsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSL.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; LSL (genzipop_long)

+;

+;

+;

+(define_insn "ashlsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "LSL\t%2,%0     ; ashlsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashlsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "LSL\t%1,%0     ; ashlsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "ashlsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "ashlsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (ashift:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSL.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; LSR (genzipop_long)

+;

+;

+;

+(define_insn "lshrsi3"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")

+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "LSR\t%2,%0     ; lshrsi3"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "lshrsi3_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "LSR\t%1,%0     ; lshrsi3_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "lshrsi3_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]

+       ""      ; Condition

+       "LSR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; LSR (genzipop_long)

+;

+;

+;

+(define_insn "lshrsi3_off"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")

+                       (plus:SI (match_operand:SI 2 "register_operand" "r")

+                               (match_operand:SI 3 "const_int_operand" "N"))))

+       (clobber (reg:CC CC_REG))]

+       ""

+       "LSR\t%2,%0     ; lshrsi3_off"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "lshrsi3_off_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N"))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       ""

+       "LSR\t%1,%0     ; lshrsi3_off_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "lshrsi3_off_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.Z\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_off_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.NZ\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_off_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.LT\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_off_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.GE\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_off_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.C\t%1,%0   ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "lshrsi3_off_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (lshiftrt:SI (match_dup 0)

+                       (plus:SI (match_operand:SI 1 "register_operand" "r")

+                               (match_operand:SI 2 "const_int_operand" "N")))))]

+       ""      ; Condition

+       "LSR.NC\t%1,%0  ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; MPYSHI (genzipop_long)

+;

+;

+;

+(define_insn "smulsi_highpart"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))

+                       (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_HAS_DI)"

+       "MPYSHI\t%2,%0  ; smulsi_highpart"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "smulsi_highpart_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_HAS_DI)"

+       "MPYSHI\t%1,%0  ; smulsi_highpart_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "smulsi_highpart_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.Z\t%1,%0        ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "smulsi_highpart_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.NZ\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "smulsi_highpart_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.LT\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "smulsi_highpart_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.GE\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "smulsi_highpart_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.C\t%1,%0        ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "smulsi_highpart_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (sign_extend:DI (match_dup 0))

+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYSHI.NC\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+;

+; MPYUHI (genzipop_long)

+;

+;

+;

+(define_insn "umulsi_highpart"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))

+                       (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))

+       (clobber (reg:CC CC_REG))]

+       "(ZIP_HAS_DI)"

+       "MPYUHI\t%2,%0  ; umulsi_highpart"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "umulsi_highpart_raw"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32))))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]

+       "(ZIP_HAS_DI)"

+       "MPYUHI\t%1,%0  ; umulsi_highpart_raw"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])

+;

+;

+(define_insn "umulsi_highpart_eq"

+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.Z\t%1,%0        ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "umulsi_highpart_ne"

+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.NZ\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "umulsi_highpart_lt"

+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.LT\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "umulsi_highpart_ge"

+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.GE\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "umulsi_highpart_ltu"

+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.C\t%1,%0        ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "umulsi_highpart_geu"

+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))

+                       (set (match_operand:SI 0 "register_operand" "=r")

+               (truncate:SI (ashiftrt:DI (mult:DI

+                       (zero_extend:DI (match_dup 0))

+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))

+                       (const_int 32)))))]

+       "(ZIP_HAS_DI)"  ; Condition

+       "MPYUHI.NC\t%1,%0       ; genzip, conditional operator" ; Template

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+;

+;

+; Conditional move instructions

+;

+;

+;

+;

+(define_insn "cmov_eq"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.Z   %1,%0   ; cmov

+       LW.Z    %1,%0   ; cmov

+       LDI.Z   %1,%0   ; cmov

+       SW.Z    %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cmov_ne"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.NZ  %1,%0   ; cmov

+       LW.NZ   %1,%0   ; cmov

+       LDI.NZ  %1,%0   ; cmov

+       SW.NZ   %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cmov_lt"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.LT  %1,%0   ; cmov

+       LW.LT   %1,%0   ; cmov

+       LDI.LT  %1,%0   ; cmov

+       SW.LT   %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cmov_ge"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.GE  %1,%0   ; cmov

+       LW.GE   %1,%0   ; cmov

+       LDI.GE  %1,%0   ; cmov

+       SW.GE   %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cmov_ltu"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.C   %1,%0   ; cmov

+       LW.C    %1,%0   ; cmov

+       LDI.C   %1,%0   ; cmov

+       SW.C    %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cmov_geu"

+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")

+                       (match_dup 0)))]

+       ""

+       "@

+       MOV.NC  %1,%0   ; cmov

+       LW.NC   %1,%0   ; cmov

+       LDI.NC  %1,%0   ; cmov

+       SW.NC   %1,%0   ; cmov"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional add instructions

+;

+;

+;

+;

+(define_insn "cadd_eq"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.Z  %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cadd_ne"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.NZ %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cadd_lt"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.LT %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cadd_ge"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.GE %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cadd_ltu"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.C  %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cadd_geu"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (plus:SI (match_dup 0)

+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "ADD.NC %1,%0   ; cadd"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional negate instructions

+;

+;

+;

+;

+(define_insn "cneg_eq"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.Z  %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cneg_ne"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.NZ %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cneg_lt"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.LT %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cneg_ge"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.GE %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cneg_ltu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.C  %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cneg_geu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (neg:SI (match_dup 0))

+                       (match_dup 0)))]

+       ""

+       "NEG.NC %0      ; cneg"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional not instructions

+;

+;

+;

+;

+(define_insn "cnot_eq"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.Z  %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cnot_ne"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.NZ %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cnot_lt"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.LT %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cnot_ge"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.GE %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cnot_ltu"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.C  %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cnot_geu"

+       [(set (match_operand:SI 0 "register_operand" "=r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0)

+                               (const_int -1))

+                       (match_dup 0)))]

+       ""

+       "NOT.NC %0      ; cnot"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional and instructions

+;

+;

+;

+;

+(define_insn "cand_eq"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.Z  %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cand_ne"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.NZ %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cand_lt"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.LT %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cand_ge"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.GE %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cand_ltu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.C  %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cand_geu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "AND.NC %1,%0   ; cand"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional ior instructions

+;

+;

+;

+;

+(define_insn "cior_eq"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.Z   %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cior_ne"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.NZ  %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cior_lt"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.LT  %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cior_ge"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.GE  %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cior_ltu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.C   %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cior_geu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "OR.NC  %1,%0   ; cior"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+; Conditional xor instructions

+;

+;

+;

+;

+(define_insn "cxor_eq"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.Z  %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cxor_ne"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.NZ %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cxor_lt"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.LT %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cxor_ge"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.GE %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cxor_ltu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.C  %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

+;

+;

+(define_insn "cxor_geu"

+       [(set (match_operand:SI 0 "register_operand" "+r")

+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))

+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))

+                       (match_dup 0)))]

+       ""

+       "XOR.NC %1,%0   ; cxor"

+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-peephole.md gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md

--- gcc-6.2.0/gcc/config/zip/zip-peephole.md    1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md        2017-03-01 15:46:02.440221158 -0500

@@ -0,0 +1,768 @@

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Filename:   zip-peephole.md

+;;

+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core

+;;

+;; Purpose:    This is a machine description of a variety of peephole

+;;             optimizations which can be applied to the ZipCPU RTL

+;;     representation.

+;;

+;;

+;; Creator:    Dan Gisselquist, Ph.D.

+;;             Gisselquist Technology, LLC

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC

+;;

+;; This program is free software (firmware): you can redistribute it and/or

+;; modify it under the terms of  the GNU General Public License as published

+;; by the Free Software Foundation, either version 3 of the License, or (at

+;; your option) any later version.

+;;

+;; This program is distributed in the hope that it will be useful, but WITHOUT

+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

+;; for more details.

+;;

+;; License:    GPL, v3, as defined and found on www.gnu.org,

+;;             http://www.gnu.org/licenses/gpl.html

+;;

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;

+;

+;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;;

+;; Peephole optimizations

+;;

+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

+;

+;

+;

+;

+;

+; Match:

+;      CMP     R1,R0

+;      BGTU    lbl

+; Transform to:

+;      CMP     R0,R1

+;      BC      lbl

+;

+(define_peephole2

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 0 "register_operand")

+               (match_operand:SI 1 "register_operand")))

+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_operand 2 ""))

+                       (pc)))]

+       "(ZIP_PEEPHOLE)"

+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+(define_peephole2

+       [(match_scratch:SI 3 "=r")

+       (set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 0 "register_operand")

+               (match_operand 1 "const_int_operand")))

+       (match_dup 3)

+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_operand 2 ""))

+                       (pc)))]

+       "(ZIP_PEEPHOLE)"

+       [(set (match_dup 3) (match_dup 1))

+       (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+;(define_peephole2

+;      [(set (reg:CC CC_REG) (compare:CC

+;              (match_operand:SI 0 "register_operand")

+;              (match_operand 1 "const_int_operand")))

+;      (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))

+;                      (label_ref (match_operand 2 ""))

+;                      (pc)))]

+;      ""

+;      [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))

+;      (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))

+;                      (label_ref (match_dup 2))

+;                      (pc)))]

+;      "operands[1] = GEN_INT(INTVAL(operands[1])-1);")

+;

+;

+; Match:

+;      CMP     R1,R0

+;      BGEU    lbl

+; Transform to:

+;      CMP     1(R0),R1

+;      BC      lbl

+;

+(define_peephole2

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_operand:SI 0 "register_operand")

+               (match_operand:SI 1 "register_operand")))

+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_operand 2 ""))

+                       (pc)))]

+       "(ZIP_PEEPHOLE)"

+       [(set (reg:CC CC_REG) (compare:CC

+               (match_dup 1) (plus:SI (match_dup 0) (const_int 1))))

+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))

+                       (label_ref (match_dup 2))

+                       (pc)))]

+       "")

+;

+;

+; Match:

+;      CMP     R1,R0

+;      BGE     lbl

+; Transform to:

+;      CMP     1(R0),R1

+;      BLT     lbl

+; ... why?  when we support a BGE instruction?

+;(define_peephole2

+       ;[(set (reg:CC CC_REG) (compare:CC

+               ;(match_operand:SI 0 "register_operand")

+               ;(match_operand:SI 1 "register_operand")))

+       ;(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))

+                       ;(label_ref (match_operand 2 ""))

+                       ;(pc)))]

+       ;"(ZIP_PEEPHOLE)"

+       ;[(set (reg:CC CC_REG) (compare:CC (match_dup 1)

+                       ;(plus:SI (match_dup 0) (const_int 1))))

+                       ;(plus:SI (match_dup 0) (const_int 1))))

+       ;(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))

+       ;(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))

+                       ;(label_ref (match_dup 2))

+                       ;(label_ref (match_dup 2))

+                       ;(pc)))]

+                       ;(pc)))]

+       ;"")

+       ;"")

Line 11515...

Line 14446...

*)

*)

        echo "*** Configuration ${target} not supported" 1>&2

        echo "*** Configuration ${target} not supported" 1>&2

        exit 1

        exit 1

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cse.c gcc-6.2.0-zip/gcc/cse.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cse.c gcc-6.2.0-zip/gcc/cse.c

--- gcc-6.2.0/gcc/cse.c 2016-02-04 04:56:13.000000000 -0500

--- gcc-6.2.0/gcc/cse.c 2016-02-04 04:56:13.000000000 -0500

+++ gcc-6.2.0-zip/gcc/cse.c     2017-02-06 21:46:10.525049918 -0500

+++ gcc-6.2.0-zip/gcc/cse.c     2018-06-05 21:17:32.963050314 -0400

@@ -42,6 +42,16 @@

@@ -42,6 +42,16 @@

 #include "dbgcnt.h"

 #include "dbgcnt.h"

 #include "rtl-iter.h"

 #include "rtl-iter.h"

Line 11817...

Line 14748...

                                                tmp, tmp1);

                                                tmp, tmp1);

          delta = simplify_gen_binary (MINUS, mode, tmp0, step);

          delta = simplify_gen_binary (MINUS, mode, tmp0, step);

          delta = simplify_gen_binary (MINUS, mode, tmp1, delta);

          delta = simplify_gen_binary (MINUS, mode, tmp1, delta);

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/optabs.c gcc-6.2.0-zip/gcc/optabs.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/optabs.c gcc-6.2.0-zip/gcc/optabs.c

--- gcc-6.2.0/gcc/optabs.c      2016-02-16 10:15:40.000000000 -0500

--- gcc-6.2.0/gcc/optabs.c      2016-02-16 10:15:40.000000000 -0500

+++ gcc-6.2.0-zip/gcc/optabs.c  2017-03-01 15:46:15.660221429 -0500

+++ gcc-6.2.0-zip/gcc/optabs.c  2018-03-23 07:13:51.664427524 -0400

@@ -43,6 +43,17 @@

@@ -43,6 +43,17 @@

 #include "optabs-tree.h"

 #include "optabs-tree.h"

 #include "libfuncs.h"

 #include "libfuncs.h"

Line 11843...

Line 14774...

                struct expand_operand *ops)

                struct expand_operand *ops)

+#ifdef DO_ZIP_DEBUGS

+#ifdef DO_ZIP_DEBUGS

+fprintf(stderr, "ICODE = %d\n", icode);

+fprintf(stderr, "ICODE = %d\n", icode);

+fprintf(stderr, "NOPS  = %d\n", nops);

+fprintf(stderr, "NOPS  = %d\n", nops);

+for(int i=0; i<nops; i++) {

+for(unsigned i=0; i<nops; i++) {

+       char    str[10];

+       char    str[10];

+       sprintf(str, "Op %d: ", i);

+       sprintf(str, "Op %d: ", i);

+       zip_debug_rtx_pfx(str, ops[i].value);

+       zip_debug_rtx_pfx(str, ops[i].value);

+}

+}

+#endif

+#endif

Line 12013...

Line 14944...

-      mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;

-      mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;

+      mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;

+      mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;

       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;

       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;

       cmpnop &= mask;

       cmpnop &= mask;

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/ubsan.c gcc-6.2.0-zip/gcc/ubsan.c

--- gcc-6.2.0/gcc/ubsan.c       2016-08-12 15:57:35.000000000 -0400

+++ gcc-6.2.0-zip/gcc/ubsan.c   2017-08-23 09:29:11.196719450 -0400

@@ -1469,7 +1469,7 @@

   expanded_location xloc = expand_location (loc);

   if (xloc.file == NULL || strncmp (xloc.file, "\1", 2) == 0

-      || xloc.file == '\0' || xloc.file[0] == '\xff'

+      || xloc.file[0] == '\0' || xloc.file[0] == '\xff'

       || xloc.file[1] == '\xff')

     return false;

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/varasm.c gcc-6.2.0-zip/gcc/varasm.c

diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/varasm.c gcc-6.2.0-zip/gcc/varasm.c

--- gcc-6.2.0/gcc/varasm.c      2016-03-31 11:30:33.000000000 -0400

--- gcc-6.2.0/gcc/varasm.c      2016-03-31 11:30:33.000000000 -0400

+++ gcc-6.2.0-zip/gcc/varasm.c  2016-12-31 17:03:08.629193673 -0500

+++ gcc-6.2.0-zip/gcc/varasm.c  2016-12-31 17:03:08.629193673 -0500

@@ -2771,7 +2771,7 @@

@@ -2771,7 +2771,7 @@

Line 12036...

Line 14979...

                                  gen_int_mode (data[nelts - 1 - i], SImode));

                                  gen_int_mode (data[nelts - 1 - i], SImode));

       else

       else

        elt = GEN_INT (data[i]);

        elt = GEN_INT (data[i]);

diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config/zip/sfp-machine.h gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h

diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config/zip/sfp-machine.h gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h

--- gcc-6.2.0/libgcc/config/zip/sfp-machine.h   1969-12-31 19:00:00.000000000 -0500

--- gcc-6.2.0/libgcc/config/zip/sfp-machine.h   1969-12-31 19:00:00.000000000 -0500

+++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h       2017-01-27 12:27:05.094921759 -0500

+++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h       2018-03-23 07:16:33.779338866 -0400

@@ -0,0 +1,53 @@

@@ -0,0 +1,55 @@

+#ifndef        ZIP_SFP_MACHINE_H

+#ifndef        ZIP_SFP_MACHINE_H

+#define        ZIP_SFP_MACHINE_H

+#define        ZIP_SFP_MACHINE_H

+#define        __BIG_ENDIAN    4321

+#define        __BIG_ENDIAN    4321

+#define        __BYTE_ORDER    __BIG_ENDIAN

+#define        __BYTE_ORDER    __BIG_ENDIAN

+#include "fp-bit.h"

+#define        _FP_W_TYPE_SIZE 32

+#define        _FP_W_TYPE_SIZE 32

+#define        _FP_W_TYPE      unsigned int

+#define        _FP_W_TYPE      unsigned int

+#define        _FP_WS_TYPE     signed int

+#define        _FP_WS_TYPE     signed int

+#define        _FP_I_TYPE      long

+#define        _FP_I_TYPE      long

Line 12093...

Line 15038...

+#define        _strong_alias(name, aliasname)  \

+#define        _strong_alias(name, aliasname)  \

+       extern __typeof(name) aliasname __attribute__ ((alias (#name)));

+       extern __typeof(name) aliasname __attribute__ ((alias (#name)));

+#endif

+#endif

diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config.host gcc-6.2.0-zip/libgcc/config.host

diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config.host gcc-6.2.0-zip/libgcc/config.host

--- gcc-6.2.0/libgcc/config.host        2016-05-17 02:15:52.000000000 -0400

--- gcc-6.2.0/libgcc/config.host        2016-05-17 02:15:52.000000000 -0400

+++ gcc-6.2.0-zip/libgcc/config.host    2017-01-27 12:28:31.470410459 -0500

+++ gcc-6.2.0-zip/libgcc/config.host    2018-03-23 07:31:08.573591955 -0400

@@ -197,6 +197,9 @@

@@ -197,6 +197,9 @@

 tic6x-*-*)

 tic6x-*-*)

        cpu_type=c6x

        cpu_type=c6x

;;

;;

+zip*)

+zip*)

Line 12109...

Line 15054...

@@ -1328,6 +1331,10 @@

@@ -1328,6 +1331,10 @@

        tmake_file="$tmake_file nvptx/t-nvptx"

        tmake_file="$tmake_file nvptx/t-nvptx"

        extra_parts="crt0.o"

        extra_parts="crt0.o"

;;

;;

+zip*)

+zip*)

+       tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp"

+       tmake_file="$tmake_file t-softfp-sfdf t-softfp t-fdpbit"

+       # extra_parts="crt0.o"

+       # extra_parts="crt0.o"

+       ;;

+       ;;

*)

*)

        echo "*** Configuration ${host} not supported" 1>&2

        echo "*** Configuration ${host} not supported" 1>&2

        exit 1

        exit 1

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[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Diff between revs 202 and 209