| Line 12... | Line 12... | 
      
        | ;       + -     (x= 22,y=-4,R0=-5,R1= 2)
 | ;       + -     (x= 22,y=-4,R0=-5,R1= 2)
 | 
      
        | ;       - -     (x=-22,y=-4,R0= 5,R1=-2)
 | ;       - -     (x=-22,y=-4,R0= 5,R1=-2)
 | 
      
        | ;
 | ;
 | 
      
        | ;
 | ;
 | 
      
        | ;
 | ;
 | 
      
        | divs:   ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1
 | lib_divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1
 | 
      
        |         SUB     2,SP
 |         SUB     2,SP
 | 
      
        |         ; (stall)
 |         STO     R2,(SP)
 | 
      
        |         STO     R3,2(SP)
 |         STO     R3,2(SP)
 | 
      
        |         ;
 |         ;
 | 
      
        |         CLR     R3              ; Keep track of resulting sign in R2
 |         CLR     R3              ; Keep track of resulting sign in R2
 | 
      
        |         TST     -1,R0           ; Is R0 negative?
 |         TST     -1,R0           ; Is R0 negative?
 | 
      
        |         MOV     ret_div32s(PC),R2
 |         MOV     ret_div32s(PC),R2
 | 
      
        | Line 27... | Line 27... | 
      
        |         MOV.LT  divu_divs_return(PC),R2
 |         MOV.LT  divu_divs_return(PC),R2
 | 
      
        |         TST     -1,R1           ; Is R1 negative?
 |         TST     -1,R1           ; Is R1 negative?
 | 
      
        |         XOR.LT  1,R3            ; If so, result will be opposite sign of before
 |         XOR.LT  1,R3            ; If so, result will be opposite sign of before
 | 
      
        |         NEG.LT  R1              ; Now we get R1=ABS(R1)
 |         NEG.LT  R1              ; Now we get R1=ABS(R1)
 | 
      
        |         MOV.LT  divu_divs_return(PC),R2
 |         MOV.LT  divu_divs_return(PC),R2
 | 
      
        |         STO     R2,1(SP)
 |         BRA     lib_divu        ; Do our unsigned multiply
 | 
      
        |         BRA     divu            ; Do our unsigned multiply
 |   | 
      
        |         ; JSR   divu            ; Do our unsigned multiply
 |         ; JSR   divu            ; Do our unsigned multiply
 | 
      
        | divu_divs_return:
 | divu_divs_return:
 | 
      
        |         TST     1,R3            ; Check resulting sign
 |         TST     1,R3            ; Check resulting sign
 | 
      
        |         NEG.NE  R0              ; Need to flip the sign of our result
 |         NEG.NE  R0              ; Need to flip the sign of our result
 | 
      
        |         TST     2,R3            ; Now, if R1 was originally negative
 |         TST     2,R3            ; Now, if R1 was originally negative
 | 
      
        |         NEG.NE  R1              ; Then negate R1
 |         NEG.NE  R1              ; Then negate R1
 | 
      
        | ret_div32s:
 | ret_div32s:
 | 
      
        |   |         LOD     (SP),R2
 | 
      
        |         LOD     2(SP),R3
 |         LOD     2(SP),R3
 | 
      
        |         LOD     3(SP),R2
 |   | 
      
        |         ADD     2,SP
 |         ADD     2,SP
 | 
      
        |         JMP     R2
 |         JMP     R2
 | 
      
        |  
 |  
 |