| Line 6... |
Line 6... |
;
|
;
|
; Purpose: Zip assembly file for running doing an unsigned divide.
|
; Purpose: Zip assembly file for running doing an unsigned divide.
|
; This routine is also called by the signed divide.
|
; This routine is also called by the signed divide.
|
;
|
;
|
; Creator: Dan Gisselquist, Ph.D.
|
; Creator: Dan Gisselquist, Ph.D.
|
; Gisselquist Tecnology, LLC
|
; Gisselquist Technology, LLC
|
;
|
;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;
|
;
|
; Copyright (C) 2015, Gisselquist Technology, LLC
|
; Copyright (C) 2015, Gisselquist Technology, LLC
|
;
|
;
|
| Line 30... |
Line 30... |
;
|
;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
;
|
;
|
;
|
;
|
;
|
;
|
divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
|
lib_divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
|
TST -1,R1
|
TST -1,R1
|
; BNZ divu_valid_divide
|
; BNZ divu_valid_divide
|
CLR.Z R0 ; Should be a divide by zero error / trap
|
CLR.Z R0 ; Should be a divide by zero error / trap
|
RETN.Z
|
JMP.Z R2
|
divu_valid_divide:
|
divu_valid_divide:
|
SUB 1,SP
|
SUB 2,SP
|
|
STO R2,(SP)
|
STO R3,1(SP)
|
STO R3,1(SP)
|
;
|
;
|
LDI 1,R2 ; Here's where we record the bit we are working on
|
LDI 1,R2 ; Here's where we record the bit we are working on
|
CLR R3 ; Here's where we build our result
|
CLR R3 ; Here's where we build our result
|
; Our original loop rejoin point, before a touch of unrolling
|
; Our original loop rejoin point, before a touch of unrolling
|
| Line 120... |
Line 121... |
BNZ divu_next_loop
|
BNZ divu_next_loop
|
|
|
divu_record_result:
|
divu_record_result:
|
MOV R0,R1
|
MOV R0,R1
|
MOV R3,R0
|
MOV R3,R0
|
|
LOD (SP),R2
|
LOD 1(SP),R3
|
LOD 1(SP),R3
|
LOD 2(SP),R2
|
ADD 2,SP
|
ADD 1,SP
|
|
JMP R2
|
JMP R2
|
|
|
