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Line 7... |
; Purpose: Zip assembly file for running a 32-bit by 32-bit signed
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; Purpose: Zip assembly file for running a 32-bit by 32-bit signed
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; multiply. It works by adjusting the sign of the 32x32-bit
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; multiply. It works by adjusting the sign of the 32x32-bit
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; unsigned multiply.
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; unsigned multiply.
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;
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;
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; Creator: Dan Gisselquist, Ph.D.
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; Creator: Dan Gisselquist, Ph.D.
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; Gisselquist Tecnology, LLC
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; Gisselquist Technology, LLC
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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;
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Line 39... |
; R1 - Second multiplicand
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; R1 - Second multiplicand
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; R2 - Comes in as scratch
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; R2 - Comes in as scratch
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; R3 - used as scratch internally
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; R3 - used as scratch internally
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mpy32s:
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mpy32s:
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ADD 2,SP
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ADD 2,SP
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STO R2,(SP)
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STO R3,2(SP)
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STO R3,2(SP)
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;
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;
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CLR R3 ; Keep track of resulting sign in R2
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CLR R3 ; Keep track of resulting sign in R2
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TST R0 ; Is R0 negative?
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TST -1,R0 ; Is R0 negative?
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XOR.LT #1,R3 ; If so, resulting sign will be negative, and
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XOR.LT 1,R3 ; If so, resulting sign will be negative, and
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NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0))
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NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0))
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TST R1 ; Is R1 negative?
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TST -1,R1 ; Is R1 negative?
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XOR.LT #1,R3 ; If so, result will be opposite sign of before
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XOR.LT 1,R3 ; If so, result will be opposite sign of before
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NEG.LT R1 ; Now we get R1=ABS(R1)
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NEG.LT R1 ; Now we get R1=ABS(R1)
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; JSR mpy32u
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; JSR mpy32u
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MOV __HERE__+2,R2 ; Do our unsigned multiply
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MOV __HERE__+2(PC),R2 ; Do our unsigned multiply
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STO R2,1(SP)
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BRA mpy32u
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BRA mpy32u
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;
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;
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TST 0,R3 ; Check resulting sign
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TST -1,R3 ; Check resulting sign
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BZ ret_mul32s ; If positive, do nothing more
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BZ ret_mul32s ; If positive, do nothing more
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NOT R0 ; If negative, negate the result
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NOT R0 ; If negative, negate the result
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NOT R1
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NOT R1
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ADD $1,R1
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ADD $1,R1
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ADD.C $1,R0
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ADD.C $1,R0
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ret_mul32s:
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ret_mul32s:
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LOD (SP),R2
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LOD 2(SP),R3
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LOD 2(SP),R3
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LOD 3(SP),R2
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ADD 2,SP
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ADD 2,SP
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JMP R2
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JMP R2
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